JPS60165752A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS60165752A JPS60165752A JP59021097A JP2109784A JPS60165752A JP S60165752 A JPS60165752 A JP S60165752A JP 59021097 A JP59021097 A JP 59021097A JP 2109784 A JP2109784 A JP 2109784A JP S60165752 A JPS60165752 A JP S60165752A
- Authority
- JP
- Japan
- Prior art keywords
- film
- signal lines
- lines
- differential
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は半導体集積回路に関し、特に差動増幅器を含む
半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit including a differential amplifier.
(従来技術)
半導体集積回路は、大規模化が進むにつれてパターンの
微細化、多層化及び回路のダイナミック化が進み、差動
増幅回路を含むものが多くなってきた。(Prior Art) As the scale of semiconductor integrated circuits increases, patterns become finer, multilayered, and circuits become more dynamic, and more and more semiconductor integrated circuits include differential amplifier circuits.
第1図(al 、 (b)は従来のMO8型集積回路の
一例の平面図及び断面図である。FIGS. 1A and 1B are a plan view and a sectional view of an example of a conventional MO8 type integrated circuit.
第1図(al 、 (b)において、1は信号線を形成
する金属配線層、2はグランド又は電源を形成する金属
配線層、3はN型拡散層、4は金属配線層と拡散層との
コンタクト、5はトランジスタのゲートや層間絶縁膜を
形成するシリコンの酸化膜、6はパッシベーションと呼
ばれる保護膜で、通常はシリコンの酸化膜、窒化膜、す
/ガラス等が使われる。7はクリコン基板でおる。In FIG. 1 (al, (b)), 1 is a metal wiring layer forming a signal line, 2 is a metal wiring layer forming a ground or power source, 3 is an N-type diffusion layer, and 4 is a metal wiring layer and a diffusion layer. 5 is a silicon oxide film that forms the transistor gate and interlayer insulating film, 6 is a protective film called passivation, and silicon oxide film, nitride film, glass, etc. are usually used. 7 is a silicon oxide film. It's on the board.
第2図は従来の差動増幅回路の一例の回路図である。FIG. 2 is a circuit diagram of an example of a conventional differential amplifier circuit.
第2図において゛、Q1〜Q6はMOSFET、D。In Fig. 2, Q1 to Q6 are MOSFETs D.
Dは差動信号線、Pは差動増幅器のプリチャージ信号線
、Sは差動増幅器の開始信号線である。D is a differential signal line, P is a precharge signal line of the differential amplifier, and S is a start signal line of the differential amplifier.
こうした集積回路は、大規模が進むにつれてパターンの
微細化が行なわれるが、各層の厚さ方向の変化は金属配
線層のエレクトロマイグレーンヨ7等の信頼性確保のた
めにほとんど変化しない。As the scale of such integrated circuits increases, the patterns become finer, but changes in the thickness direction of each layer hardly change in order to ensure the reliability of the electromigrain layer 7 of the metal wiring layer.
従って、通常のプリ7ト板と異って、電気力線の影響で
隣接配線間の容量が増大する。例えば、256キロビツ
トメモリ程度のパターンでは隣接配線間容量は全配線容
量の20チくらいになる。従って、隣接する配線で一方
の信号線の電位が変化すると他方の信号線に雑音を生じ
る。この雑音は、例えば差動信号線の一方に生じると差
動増幅器の誤動作を引起こす場合がある。こうした問題
の対策として、通常はグランド電位を印加された層を上
下に形成した遮蔽が考えられるが、集積回路では多層化
は不利である。このように、差動増幅器を含む半導体集
積回路では、雑音を生じやすいかあるいは雑音を防ごう
とすると製造において不利となるという欠点がおった。Therefore, unlike a normal printed circuit board, the capacitance between adjacent wirings increases due to the influence of electric lines of force. For example, in a pattern for a 256 kilobit memory, the capacitance between adjacent wires is about 20 inches of the total wire capacitance. Therefore, if the potential of one signal line in adjacent wirings changes, noise will occur in the other signal line. If this noise occurs on one side of the differential signal line, for example, it may cause malfunction of the differential amplifier. As a countermeasure to this problem, shielding is usually considered in which layers to which a ground potential is applied are formed above and below, but multi-layering is disadvantageous in integrated circuits. As described above, semiconductor integrated circuits including differential amplifiers have the disadvantage that they tend to generate noise or that attempts to prevent noise are disadvantageous in manufacturing.
(発明の目的)
本発明の目的は、上記欠点を除去し、差動信号線に引起
される雑音を低減し安定に動作する差動増幅回路を含む
半導体集積回路を提供することにある。(Object of the Invention) An object of the present invention is to provide a semiconductor integrated circuit including a differential amplifier circuit that eliminates the above drawbacks, reduces noise caused in differential signal lines, and operates stably.
(発明の構成)
本発明の半導体集積回路は、差動増幅回路を含む半導体
集積回路において、前記差動増幅回路の2本の差動信号
線を平行に隣り合って形成し、その両外側に低抵抗体で
相互に短絡された2本の配線をそれぞれ配置することに
より構成される。(Structure of the Invention) A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit including a differential amplifier circuit, in which two differential signal lines of the differential amplifier circuit are formed adjacent to each other in parallel, and It is constructed by arranging two wires that are short-circuited to each other using a low-resistance material.
(実施例) 次に本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第3図(al 、 (blは本発明の一実施例の平面図
及び断面図である。FIG. 3 (al and bl are a plan view and a sectional view of an embodiment of the present invention.
この実施例は、差動増幅回路を含む半導体集積回路にお
いて、差動増幅回路の2本の差動信号線8R、8Lを平
行に隣り合って形成し、その両外側に低抵抗体で相互に
短絡された2本の配線2R。In this embodiment, in a semiconductor integrated circuit including a differential amplifier circuit, two differential signal lines 8R and 8L of the differential amplifier circuit are formed adjacent to each other in parallel, and a low resistance material is placed on both outer sides of the two differential signal lines 8R and 8L. Two shorted wires 2R.
2Lをそれぞれ配置することにより構成される。It is constructed by arranging 2L respectively.
更に詳しく説明すると、配線2R22Lは金属などの導
体で形成され、例えば図示するように。To explain in more detail, the wiring 2R22L is formed of a conductor such as metal, for example, as shown in the figure.
コンタクト4全通して低抵抗体の拡散層3で互いに短絡
され、同電位に保たれる。この実施例では拡散層3で短
絡しであるが、他の手段で短絡しても良い。要は同電位
に保たれることが重要なのである。All of the contacts 4 are short-circuited to each other by the low-resistance diffusion layer 3 and kept at the same potential. In this embodiment, the short circuit is made by the diffusion layer 3, but the short circuit may be made by other means. In short, it is important to maintain the same potential.
尚、IR,ILは信号線、5はシリコン酸化膜。Note that IR and IL are signal lines, and 5 is a silicon oxide film.
6・は保護膜、7はシリコン基板でめる。6 is a protective film, and 7 is a silicon substrate.
この実施例において、信号線IRの電位を急激に変化さ
せた場合、信号線IRと2Rとの間に形成される容量の
ために信号線2Rに雑音を生じるが、信号線2Lも同電
位であるため、差動信号線8R,8Lには同様の雑音を
生じる。そのため、差動信号線8R,8Lの差動値は変
化しない。配線2R,2T、はシールドのために配置す
るだけでなく、通常の信号線、電源線などにも使用でき
る。In this embodiment, when the potential of the signal line IR is suddenly changed, noise is generated on the signal line 2R due to the capacitance formed between the signal line IR and 2R, but the signal line 2L is also at the same potential. Therefore, similar noise occurs in the differential signal lines 8R and 8L. Therefore, the differential value of the differential signal lines 8R and 8L does not change. The wirings 2R and 2T are not only arranged for shielding, but can also be used as normal signal lines, power supply lines, etc.
配線2J 2Lは、パターンの微細化が進むとさほどチ
ップ面積の増大に影響を与えないし、新たな工程を追加
することなく追加できる。The wirings 2J to 2L do not significantly affect the increase in chip area as the pattern becomes finer, and can be added without adding any new process.
(発明の効果)
以上詳細に説明したように、本発明によれば、差動信号
線に引起される雑音を低減し安定動作する差動増幅回路
を含む半導体集積回路が得られる。(Effects of the Invention) As described in detail above, according to the present invention, it is possible to obtain a semiconductor integrated circuit including a differential amplifier circuit that reduces noise caused in differential signal lines and operates stably.
5−5-
第1図(a) 、 (b)は従来のMO8集積回路の一
例の平面図及び断面図、第2図は従来の差動増幅回路の
一例の回路図、第3図(a)、Φ)は本発明の一実施例
の平面図及び断面図である。
1 、IR,IL・・・・・・信号線、2・・・・・・
金属配線層(定電位源接続用)、2R,ZL・・・・・
・配線、3・・・用拡散層、4・・・・・・コンタクト
、5・・・・・・シリコン酸化膜、6・・・・・・保護
膜、7・・・・・・シリコン基板、8R18L・・・・
・・差動信号線、D、D・・・・・・差動信号線、P・
・・・・・プリチャージ信号線、S・・・・・・開始信
号線。
6−
(久フ
(17)
事2圀
255−Figures 1 (a) and (b) are a plan view and a cross-sectional view of an example of a conventional MO8 integrated circuit, Figure 2 is a circuit diagram of an example of a conventional differential amplifier circuit, and Figure 3 (a) and Φ). 1 is a plan view and a sectional view of an embodiment of the present invention. 1, IR, IL...signal line, 2...
Metal wiring layer (for constant potential source connection), 2R, ZL...
・Wiring, 3... diffusion layer, 4... contact, 5... silicon oxide film, 6... protective film, 7... silicon substrate , 8R18L...
...Differential signal line, D, D...Differential signal line, P...
...Precharge signal line, S...Start signal line. 6- (Kufu (17) Koto 2 Koku 255-
Claims (1)
増幅回路の2本の差動信号線を平行に隣り合って形成し
、その両外側に低抵抗体で相互に短絡された2本の配線
をそれぞれ配置したことを特徴とする半導体集積回路。In a semiconductor integrated circuit including a differential amplifier circuit, two differential signal lines of the differential amplifier circuit are formed adjacent to each other in parallel, and two wirings are short-circuited to each other with a low resistance material on both outsides thereof. A semiconductor integrated circuit characterized in that each of these is arranged.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59021097A JPS60165752A (en) | 1984-02-08 | 1984-02-08 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59021097A JPS60165752A (en) | 1984-02-08 | 1984-02-08 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60165752A true JPS60165752A (en) | 1985-08-28 |
Family
ID=12045365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59021097A Pending JPS60165752A (en) | 1984-02-08 | 1984-02-08 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60165752A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5050238A (en) * | 1988-07-12 | 1991-09-17 | Sanyo Electric Co., Ltd. | Shielded front end receiver circuit with IF amplifier on an IC |
US5155570A (en) * | 1988-06-21 | 1992-10-13 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit having a pattern layout applicable to various custom ICs |
US5160997A (en) * | 1988-08-12 | 1992-11-03 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with shield electrodes for protecting the interconnection lines from undesirable radiation |
WO2023162814A1 (en) * | 2022-02-28 | 2023-08-31 | ローム株式会社 | Amplifier, amplification circuit, and current detection device |
-
1984
- 1984-02-08 JP JP59021097A patent/JPS60165752A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155570A (en) * | 1988-06-21 | 1992-10-13 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit having a pattern layout applicable to various custom ICs |
US5050238A (en) * | 1988-07-12 | 1991-09-17 | Sanyo Electric Co., Ltd. | Shielded front end receiver circuit with IF amplifier on an IC |
US5160997A (en) * | 1988-08-12 | 1992-11-03 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with shield electrodes for protecting the interconnection lines from undesirable radiation |
WO2023162814A1 (en) * | 2022-02-28 | 2023-08-31 | ローム株式会社 | Amplifier, amplification circuit, and current detection device |
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