JP3302810B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is suitable for noise suppression in a semiconductor device.

[0002]

2. Description of the Related Art FIGS. 1 and 2 show a conventional method of blocking noise in a semiconductor device. The former is a method of blocking noise sources. That is, the GDN line 3 is formed on the Si semiconductor substrate 4 at the center of the signal lines 1 and 2 which are parallel to each other as shown in FIG. 1, and the signal line 1 and the GDN line are formed on the Si semiconductor substrate 4 as shown in FIG. An example in which 3 intersect in a bridge shape is known, and FIG. 2 is an example in which noise is prevented from jumping in, and intersects a plurality of times.

[0003]

In such a conventional technique, since the circuit wiring is exposed on the Si semiconductor substrate 4, it becomes a source of noise.

Further, since the circuit wiring is exposed on the Si semiconductor substrate 4, it is easily affected as a noise antenna.

Furthermore, since the thickness of the metal layer used for the wiring is thin, it is strong against two-dimensional noise but weak against three-dimensional electromagnetic induction.

The present invention has been made in view of such circumstances, and in particular, provides a novel semiconductor device for preventing generation or jump of noise in a circuit made of a semiconductor element.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
An integrated circuit formed on the semiconductor substrate and having pads arranged therearound; a sealing resin layer covering substantially the entire surface of the integrated circuit except for the pad portion; and a metal layer, comprising a connecting portion for electrically connecting the metal layer on the integrated circuit, the integrated circuit includes a plurality
Constructed from a circuit, the sealing resin layer and the metal layer, prior to
It is characterized by being provided in each of the plurality of circuits .

Further , in the semiconductor device according to the present invention, the metal layer
Is made of a material different from the wiring forming the integrated circuit.
It is characterized by having been done.

[0009]

According to the present invention, the entire circuit portion of the semiconductor device is covered with a metal layer made of a material different from that of the wiring, and this is grounded.
And a low impedance connection such as a power supply. Further, a so-called pad or the like electrically connected to an external electronic device is not covered with a metal layer, but an opening is provided so that electrical connection to the electronic device can be performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to FIGS. In one embodiment shown in FIG. 3, one or a plurality of elements selected from the group consisting of an active element and a passive element are incorporated into, for example, a Si semiconductor substrate 10 to constitute an integrated circuit element. It is formed by a circuit or a linear circuit. That is, after a linear circuit constituting an integrated circuit element is built, a pad (A) serving as a connection terminal with an external electronic device is provided on the peripheral end of the Si semiconductor substrate 10, for example.
(l-Si, Al-Si-Cu) 11 is formed by a patterning process using a lithography method, and a GND or power supply pad 12 is formed as one of them.

This logic circuit covers a sealing resin layer by a so-called transfer molding method, and has a metal layer 1 made of a metal foil having a thickness of 0.1 mm to 0.01 mm on the surface thereof.
After being attached, 3 is electrically connected to a GND pad or a power supply 12 constituting a low-impedance connection portion, thereby preventing generation of noise and jumping.

Further, in FIG. 4, for example, a Si semiconductor substrate 10 incorporating a linear circuit 14 forming an integrated circuit element is shown.
Pads that serve as connection terminals for external electronic devices
(Al-Si, Al-Si-Cu) 11 is formed by the patterning process using the lithography method as described above, and a GND or power supply pad 12 is provided as one of them.
The linear circuit is composed of one or more types selected from the group consisting of active elements and passive elements, and its surface is covered with a sealing resin layer formed by transfer molding,
Further, a metal layer 13 made of a metal foil having a thickness of 0.1 mm to 0.01 mm is applied to the surface.

This is electrically connected to a GND pad or a power supply pad 12 constituting a low-impedance connection part, thereby preventing generation and jump of noise.

FIG. 5 shows the logic circuit 14 and the linear circuit 1.
The example of the integrated circuit in which 5 is mixed is clarified. These two circuits are configured by, for example, incorporating one or more types selected from the group consisting of active elements and passive elements into the Si semiconductor substrate 10, and the peripheral end of the Si semiconductor substrate 10 serves as a connection terminal for electronic devices. A pad (Al-Si, Al-Si-Cu) 11 is formed by a patterning process using a lithography method, and one of the pads is used as a GND or power supply pad 12.

Further, as described above, the surface of such an integrated circuit is covered with a sealing resin layer formed by a transfer molding method, and the surface is further formed of a metal foil having a thickness of 0.1 mm to 0.01 mm. After each circuit is covered with the metal layer 13, it is connected to a GND pad for a linear circuit or a pad 12 for a power supply or a GND for a logic circuit or a pad 12 for a power supply, which constitutes a low-impedance connection part, thereby preventing noise from jumping in. I do.

[0016]

In such a semiconductor device,
I. No noise is generated for the integrated circuit. Not receive noise from outside the integrated circuit; c. Advantages such as that each circuit signal does not jump into a circuit mixed in one integrated circuit are exhibited.

[0017] In such recent semiconductor element, particularly MOS transistor is promoting the 3v of, tend to be smaller V _{h f.} Therefore it is easy to make noise and pick it up,
Shrinking tends to increase Gm. The semiconductor device according to the present invention is extremely effective for such a semiconductor element.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method of shutting off a noise source in a conventional semiconductor device.

FIG. 2 is a diagram showing a structure of a conventional semiconductor element for preventing noise from entering.

FIG. 3 is a top view of the semiconductor device according to the present invention.

FIG. 4 is a top view of another semiconductor device according to the present invention.

FIG. 5 is a top view of still another semiconductor device according to the present invention.

[Explanation of symbols]

 1, 2: signal line, 3: GND line, 4, 10: semiconductor substrate, 11: pad, 12: GND or power supply pad, 13: metal layer, 14: logic circuit, 15: linear circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04

Claims (2)

(57) [Claims] 1. A formed on the semiconductor substrate, the pads around
And arranged integrated circuit, the pad portion of the integrated circuit
Almost a sealing resin layer covering the entire surface, the sealing resin layer, excluding
A metal layer which is substantially entirely in the laminated formation, before the metal layer
; And a connection portion electrically connected to the serial integrated circuit, wherein
The integrated circuit is composed of a plurality of circuits , and the sealing resin layer and the
And the metal layer is provided on each of the plurality of circuits
A semiconductor device. 2. The circuit according to claim 1, wherein the metal layer is a wiring that forms the integrated circuit.
Characterized by being made of a material different from the wire
The semiconductor device according to claim 1.