JPH06318597A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06318597A
JPH06318597A JP10578793A JP10578793A JPH06318597A JP H06318597 A JPH06318597 A JP H06318597A JP 10578793 A JP10578793 A JP 10578793A JP 10578793 A JP10578793 A JP 10578793A JP H06318597 A JPH06318597 A JP H06318597A
Authority
JP
Japan
Prior art keywords
conductive film
power supply
semiconductor device
power
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10578793A
Other languages
Japanese (ja)
Inventor
Kenji Itami
健司 板見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP10578793A priority Critical patent/JPH06318597A/en
Publication of JPH06318597A publication Critical patent/JPH06318597A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225Shielding layers formed together with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223Capacitor integral with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To realize high speed operation of a circuit, by a method wherein the influence of external noise is reduced by forming one or many layers of conductive films covering a greater part of an element, on the uppermost layer of a semiconductor device, and constituting electrostatic shielding, internal noise is reduced by adding a smoothing capacitor, and the conductive layers are used as power supply wirings. CONSTITUTION:A conductive film 7 and a second conductive film 8 are formed on the uppermost layer part of a substrate 1, and connected with a power supply side lead frame 5 and a ground side lead frame 6. These conductive films are used as a power supply smoothing capacitor, an electrostatic shielding plate, and an electromagnetic shielding plate. By electrically connecting the conductive films with a circuit, the conductive films can be used as the power supply wiring, which stably supply power and reduce the influence of external noise upon internal circuits. When a single layer of the conductive film 7 is formed, it has the effect of electrostatic shielding and that of electromagnetic shielding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に雑音防止、高速動作技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to noise prevention and high speed operation technology.

【0002】[0002]

【従来の技術】従来の半導体装置の断面概略を図2に示
す。従来の半導体装置では図2に示す様に、半導体基板
1は保護膜3と樹脂性パッケージ4で封入される事で機
械的な衝撃や湿度から保護されている。また、電源側リ
ードフレーム5とグランド側リードフレーム6はボンデ
ィングワイヤー2を介して直接半導体基板1上の半導体
回路に電源供給を行っている。しかし一般に半導体装置
が使用される場合、半導体装置周辺の回路が発生する電
気雑音や磁気雑音、並びに電源雑音にさらされており、
半導体装置の使用者は、半導体装置の電源入力部にバイ
パスコンデンサを挿入したり、静電遮へいを施したり、
また回路レイアウトを工夫したりして周辺回路の発する
雑音を低減する必要があり、十分な知識と経験が要求さ
れていた。
2. Description of the Related Art FIG. 2 shows a schematic sectional view of a conventional semiconductor device. In the conventional semiconductor device, as shown in FIG. 2, the semiconductor substrate 1 is protected from mechanical shock and humidity by being enclosed with a protective film 3 and a resin package 4. The power supply side lead frame 5 and the ground side lead frame 6 directly supply power to the semiconductor circuit on the semiconductor substrate 1 via the bonding wires 2. However, in general, when a semiconductor device is used, it is exposed to electrical noise, magnetic noise, and power source noise generated by circuits around the semiconductor device,
The user of the semiconductor device inserts a bypass capacitor in the power input section of the semiconductor device, or provides electrostatic shielding,
In addition, it is necessary to devise the circuit layout to reduce the noise generated by the peripheral circuits, and sufficient knowledge and experience are required.

【0003】[0003]

【発明が解決しようとする課題】従来の半導体装置で
は、半導体基板上の電気回路は樹脂等を用いて物理的に
は保護されているものの、電気的にはむき出しの状態で
あり、外部からの電気雑音,磁気雑音で誤動作する可能
性が高いという問題点があった。また出力トランジスタ
を多数包含する様な半導体装置では、内部で消費する電
力が大きい為、半導体装置内部において電源供給が不足
し、この為電源からの雑音で誤動作する可能性が高いと
いう問題点があった。
In the conventional semiconductor device, although the electric circuit on the semiconductor substrate is physically protected by using a resin or the like, it is in an electrically exposed state and is not exposed from the outside. There was a problem that there is a high possibility of malfunction due to electrical noise and magnetic noise. Further, in a semiconductor device including a large number of output transistors, the power consumed internally is large, so that the power supply is insufficient inside the semiconductor device, which may cause a malfunction due to noise from the power supply. It was

【0004】本発明の目的は、半導体装置周辺の回路が
発生する電気雑音や磁気雑音、並びに電源雑音などの外
部雑音、又は内部雑音を低減でき、また回路の高速動作
に貢献できる半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device capable of reducing external noise such as electric noise and magnetic noise generated by a circuit around the semiconductor device, and external noise such as power supply noise, or internal noise, and contributing to high-speed operation of the circuit. To do.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体回路を保護する為の保護膜の上に導電性の膜を1
層、もしくは多層構成し、その導電性膜を電源又はグラ
ンド、もしくはその両方と接続することにより、静電遮
へい、電磁遮へい又は電源平滑キャパシタ、電源配線、
もしくはこれらを包含して用いることを特徴として構成
される。
The semiconductor device of the present invention comprises:
Conductive film on the protective film to protect the semiconductor circuit 1
By forming a layer or a multi-layered structure and connecting the conductive film to a power source, a ground, or both, electrostatic shielding, electromagnetic shielding or a power smoothing capacitor, power wiring,
Alternatively, it is configured to include and use these.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の実施例を説明するための断面図であ
り、図1(a)は導電性膜を1層形成した一実施例の断
面図、図1(b)は導電性膜を2層形成した他の実施例
の断面図、図1(c)は電力消費の大きい回路に直接電
源を供給した第3の実施例の断面図である。
The present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention, FIG. 1A is a cross-sectional view of one embodiment in which one conductive film is formed, and FIG. FIG. 1C is a sectional view of another embodiment in which layers are formed, and FIG. 1C is a sectional view of a third embodiment in which power is directly supplied to a circuit that consumes a large amount of power.

【0007】まず第1の実施例について説明する。図1
(a)に示すように、半導体基板1、保護膜3の上に導
電性膜7を形成し導電性膜はボンディングワイヤーを介
してグランド側のリードフレーム6と接続される。又、
導電性膜7は直接半導体基板の電源のグランドパッドに
接続するのも可能である。これにより導電性膜7は半導
体基板1に対して遮へいの効果を有することができる。
First, the first embodiment will be described. Figure 1
As shown in (a), a conductive film 7 is formed on the semiconductor substrate 1 and the protective film 3, and the conductive film is connected to the ground-side lead frame 6 via a bonding wire. or,
The conductive film 7 can be directly connected to the ground pad of the power source of the semiconductor substrate. Thereby, the conductive film 7 can have an effect of shielding the semiconductor substrate 1.

【0008】次に第2の実施例について、図1(b)を
参照して説明する。図1(b)は導電性膜を2層にし、
遮へいと同時に平滑キャパシタとして用いた場合の断面
図で、図1(a)に於ける導電性膜7の上に、7とは絶
縁された第2導電性膜8を形成し、ボンディングワイヤ
ー2を介し電源側リードフレーム5と接続する。導電性
膜7と第2導電性膜8は互いに絶縁され、電源−グラン
ド間の電位になっているので平滑キャパシタとして動作
する。また図1(a)と同時に遮へい効果も同時に併せ
持っている。
Next, a second embodiment will be described with reference to FIG. In FIG. 1B, the conductive film has two layers,
In a cross-sectional view when used as a smoothing capacitor simultaneously with shielding, a second conductive film 8 insulated from 7 is formed on the conductive film 7 in FIG. It is connected to the lead frame 5 on the power source side through. Since the conductive film 7 and the second conductive film 8 are insulated from each other and have a potential between the power supply and the ground, they operate as a smoothing capacitor. Further, it has a shielding effect at the same time as FIG.

【0009】次に、第3の実施例について図1(c)を
参照して説明する。図1(c)は第2の実施例におい
て、導電性膜7,8から出力ドランジスタ等電力消費に
大きい回路に直接電源を供給した例を示すもので、導電
性膜7から出力用ドランジスタドレイン11に電源を、
第2導電性膜8は出力用トランジスタソース10に導電
性膜7を貫通して接続されている。ここで9は出力用ト
ランジスタゲートである。大量に電力を消費する回路に
対し上記の電源供給を行うと、電源配線の寄生抵抗を減
少させることができ、平滑キャパシタの効果を直接、電
力消費の大きい回路に反映出来ることから、高速で動作
する半導体装置を実現出来る。なおこの実施例では第1
の実施例,第2の実施例の特徴を併せ持っている。
Next, a third embodiment will be described with reference to FIG. FIG. 1C shows an example in which power is directly supplied from the conductive films 7 and 8 to a circuit that consumes a large amount of power, such as the output transistors, in the second embodiment. Power to 11,
The second conductive film 8 is connected to the output transistor source 10 through the conductive film 7. Here, 9 is an output transistor gate. When the above power supply is supplied to a circuit that consumes a large amount of power, the parasitic resistance of the power supply wiring can be reduced and the effect of the smoothing capacitor can be directly reflected in the circuit that consumes a large amount of power. A semiconductor device that does In this embodiment, the first
This embodiment has the features of both the embodiment and the second embodiment.

【0010】なお上記の実施例の説明では述べなかった
が、最上層部には保護膜を形成するのが耐湿性上の観点
から望ましい。
Although not described in the above description of the embodiments, it is desirable to form a protective film on the uppermost layer from the viewpoint of moisture resistance.

【0011】[0011]

【発明の効果】以上説明したように本発明は半導体回路
上に1層もしくは2層の導電性膜を形成し、これを静電
遮へい又は2層の場合は加えて電源平滑キャパシタとし
て用いた場合、電気雑音,磁気雑音,電源からの雑音を
低減出来る事から雑音の影響を受けにくい、半導体装置
が実現出来るという結果を有する。
As described above, according to the present invention, one or two layers of conductive film are formed on a semiconductor circuit, and when this is used as an electrostatic shield or in the case of two layers, it is used as a power supply smoothing capacitor. In addition, since it is possible to reduce electric noise, magnetic noise, and noise from the power supply, it is possible to realize a semiconductor device that is not easily affected by noise.

【0012】更に導電性膜を電源配線として用いた場合
には、電源配線の寄生抵抗を減少出来るので、より高速
な半導体装置を実現出来るという結果を有する。
Further, when the conductive film is used as the power supply wiring, the parasitic resistance of the power supply wiring can be reduced, so that a faster semiconductor device can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を説明するための半導体装置の
断面図で、図1(a)は導電性膜を1層形成した一実施
例の断面図、図1(b)は導電性膜を2層形成した他の
実施例の断面図、図1(c)は導電性膜を2層形成電力
消費の大きい回路に直接電源を供給した第3の実施例の
断面図である。
1A and 1B are cross-sectional views of a semiconductor device for explaining an embodiment of the present invention. FIG. 1A is a cross-sectional view of an embodiment in which one conductive film is formed, and FIG. FIG. 1C is a cross-sectional view of another embodiment in which two layers of films are formed, and FIG. 1C is a cross-sectional view of a third embodiment in which a power is directly supplied to a circuit in which a conductive film has two layers and consumes a large amount of power.

【図2】従来の半導体装置の断面図である。FIG. 2 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 ボンディングワイヤー 3 半導体回路並びに保護膜 4 樹脂性パッケージ 5 電源側リードフレーム 6 グランド側リードフレーム 7 導電性膜 8 第2導電性膜 9 出力用トランジスタゲート 10 出力用トランジスタソース 11 出力用ドランジスタドレイン 1 Semiconductor Substrate 2 Bonding Wire 3 Semiconductor Circuit and Protective Film 4 Resin Package 5 Power Lead Frame 6 Ground Lead Frame 7 Conductive Film 8 Second Conductive Film 9 Output Transistor Gate 10 Output Transistor Source 11 Output Transistor Transistor drain

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面に所望の素子を形成し金
属配線で電気回路を構成した半導体装置において、半導
体装置の最上層部に素子の大部分をおおう導電性膜を1
層もしくは多層構成し、この導電膜を一定電位に保持す
ることにより、静電遮へい,電磁遮へい,又は電源平滑
キャパシタ,電源配線、もしくはこれらの組合せとして
用いる事を特徴とする半導体装置。
1. In a semiconductor device in which a desired element is formed on the surface of a semiconductor substrate and an electric circuit is constituted by metal wiring, a conductive film covering most of the element is formed on the uppermost layer of the semiconductor device.
A semiconductor device having a layered or multilayered structure, which is used as an electrostatic shield, an electromagnetic shield, a power supply smoothing capacitor, a power supply wiring, or a combination thereof by holding the conductive film at a constant potential.
JP10578793A 1993-05-07 1993-05-07 Semiconductor device Pending JPH06318597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10578793A JPH06318597A (en) 1993-05-07 1993-05-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10578793A JPH06318597A (en) 1993-05-07 1993-05-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06318597A true JPH06318597A (en) 1994-11-15

Family

ID=14416853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10578793A Pending JPH06318597A (en) 1993-05-07 1993-05-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06318597A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001011686A1 (en) * 1999-08-11 2001-02-15 Lewyn Consulting, Inc. High-value integrated circuit resistor
US6274224B1 (en) 1999-02-01 2001-08-14 3M Innovative Properties Company Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article
US6577492B2 (en) 2001-07-10 2003-06-10 3M Innovative Properties Company Capacitor having epoxy dielectric layer cured with aminophenylfluorenes
EP1349212A3 (en) * 2002-03-19 2004-01-21 Fujitsu Limited Semiconductor integrated circuit with a shield wiring
JP2005347488A (en) * 2004-06-02 2005-12-15 Fujitsu Ltd Semiconductor apparatus
US7051311B2 (en) * 2002-06-21 2006-05-23 Fujitsu Limited Semiconductor circuit designing method, semiconductor circuit designing apparatus, program, and semiconductor device
WO2012041889A1 (en) * 2010-09-29 2012-04-05 St-Ericsson Sa Power routing with integrated decoupling capacitance

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274224B1 (en) 1999-02-01 2001-08-14 3M Innovative Properties Company Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article
US6638378B2 (en) 1999-02-01 2003-10-28 3M Innovative Properties Company Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article
WO2001011686A1 (en) * 1999-08-11 2001-02-15 Lewyn Consulting, Inc. High-value integrated circuit resistor
US6577492B2 (en) 2001-07-10 2003-06-10 3M Innovative Properties Company Capacitor having epoxy dielectric layer cured with aminophenylfluorenes
EP1349212A3 (en) * 2002-03-19 2004-01-21 Fujitsu Limited Semiconductor integrated circuit with a shield wiring
US7411277B2 (en) 2002-03-19 2008-08-12 Fujitsu Limited Semiconductor integrated circuit having shield wiring
KR100880506B1 (en) * 2002-03-19 2009-01-28 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Shield structure for semiconductor integrated circuit
US7051311B2 (en) * 2002-06-21 2006-05-23 Fujitsu Limited Semiconductor circuit designing method, semiconductor circuit designing apparatus, program, and semiconductor device
JP2005347488A (en) * 2004-06-02 2005-12-15 Fujitsu Ltd Semiconductor apparatus
WO2012041889A1 (en) * 2010-09-29 2012-04-05 St-Ericsson Sa Power routing with integrated decoupling capacitance
CN103125020A (en) * 2010-09-29 2013-05-29 意法爱立信有限公司 Power routing with integrated decoupling capacitance

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