JPS58222546A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58222546A
JPS58222546A JP57061303A JP6130382A JPS58222546A JP S58222546 A JPS58222546 A JP S58222546A JP 57061303 A JP57061303 A JP 57061303A JP 6130382 A JP6130382 A JP 6130382A JP S58222546 A JPS58222546 A JP S58222546A
Authority
JP
Japan
Prior art keywords
wiring
layer
metal
width
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57061303A
Other languages
Japanese (ja)
Inventor
「あ」田　修二
Shuji Yanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP57061303A priority Critical patent/JPS58222546A/en
Publication of JPS58222546A publication Critical patent/JPS58222546A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PURPOSE:To prevent the light beam which is directly striking the element region of IC by forming an adequate form of metal thin film to be used for wiring, employing multi-layered wiring structure and by adequately arranging a metal thin film as the light shielding procedures. CONSTITUTION:Metal lead width is widened, not like a lead wire, as shown as 11, 12, within the layer to which it belongs as covering such layer. When a multilayered wiring structure is thus formed, gap formed in each layer is filled with metal wirings of other layers, perfectly shielding the light beam. Namely, the light beam is shielded at least at any one of the metal wirings of the first, second and third layers. Increase of floating capacitance due to widened metal wiring width can be prevented by locating a narrow width wiring just under the wide width wiring. Deterioration of integration density of IC due to widened width of lead wire can be compensated by employing multi-layered wiring structure.

Description

【発明の詳細な説明】 一般に半導体装置は光に対して電気的特性の変化が発生
ずる。そのため従来実装工程において前記特性の変化を
防ぐ遮光対策がなされる。前記遮光対策は通常セラミッ
クパッケージへの封入や樹脂モールドによって行なわれ
て来た。しかし、これらは実装工程を複雑で高価なもの
にするばかりか、遮光利料を薄くしなければならないよ
うな実装構造では、遮光効果が不十分になる恐れがある
。DETAILED DESCRIPTION OF THE INVENTION In general, semiconductor devices undergo changes in their electrical characteristics in response to light. Therefore, in the conventional mounting process, light shielding measures are taken to prevent changes in the characteristics. The above-mentioned light shielding measures have usually been taken by enclosing the device in a ceramic package or by resin molding. However, these methods not only make the mounting process complicated and expensive, but also may result in insufficient light-shielding effects in a mounting structure that requires thinning of the light-shielding material.

さらに検査工程において光による影響を十分考慮しなけ
ればならなかった。Furthermore, the influence of light had to be taken into consideration during the inspection process.

本発明はこれらの問題を解消することを目的とし光対策
をＩＣ製造における金属多層配線工程と同車に行った。The present invention aims to solve these problems by implementing optical countermeasures at the same time as the metal multilayer wiring process in IC manufacturing.

これにより実装工程における遮光対策の軽減、検育工程
における光の影響の緩和がなされる。This reduces the need for light shielding measures during the mounting process and the influence of light during the inspection process.

さらに本発明の遮光対策は配線に用（・る金属薄膜を適
当な形状にし、さらに多層配線構造を用℃・前記金属薄
膜を適当に配置することにより、ＩＣ内の素子領域に直
接入射する光を防ぐものであム以下図によって本発明の
詳細な説明する。第１図（ａ）、（　ｂ）は従来のＩＣ
を示す平面図と断面図。Furthermore, the light shielding measures of the present invention can be applied to the wiring by forming the metal thin film into an appropriate shape and using a multilayer wiring structure. The present invention will be explained in detail with reference to the following figures. Figures 1 (a) and 1 (b) are
A plan view and a sectional view showing the.

第２図（ａ）、（ｂ）は本発明によるＩＣを示す平面図
と断面図を表しており、それぞれにおいて（ａ）は平面
図（ｂ）は断面図である。第１図に於て１、はＩＣチッ
プ、２、はボンデイノグノくラド，５、は保護膜４、６
は金属配線を示している。第１図のＩＣでは金属配線４
、６は一層であり、その線幅７’Ｊ’＝狭℃・ため、こ
のま＼では光に敏感な素子を含む領域３、７に第１図（
ｂ）に示すごとく光Ａが直接入射１゛るため素子は光に
よる誤動作をすることになる。第２図は本発明の遮光対
策を施したＩＣの平面図と断面図である。第１図に於て
８はＩＣチップ、９はポンディ７グパツド、１２．１８
は第１層目の金属配線層、１１．１６は第２層目の金属
配線層、１０．１４は第３層目の金属配線層で、１５．
１７は金属配線層間の絶縁層である。第２図（ａ）から
れかるごとく各層の金属配線は第１図（、）に示す従来
の配線の如く線状ではなく１１．１２の如く、金属線１
４］をその属１−ろ層の中でできるだけ広げてその層を
覆う如く構成するものである。こうすることにより多層
配線構造を形成すれば各層にできるすき間も他の層の金
属配線によって埋められ光は完全に遮ぎられることにな
る。即ち第２図（ｂ）の実施例では第１層、第２層、第
３層の金属配線の少くともいずれかによって遮光が行わ
れること＼なる。FIGS. 2(a) and 2(b) show a plan view and a cross-sectional view of an IC according to the present invention, in which (a) is a plan view and (b) is a cross-sectional view. In Figure 1, 1 is an IC chip, 2 is a bonding layer, 5 is a protective film 4, 6
indicates metal wiring. In the IC shown in Figure 1, metal wiring 4
, 6 is a single layer, and its line width 7'J' = narrow °C. Therefore, at this point, the regions 3 and 7 containing light-sensitive elements are shown in Fig. 1 (
As shown in b), since the light A is directly incident, the element will malfunction due to the light. FIG. 2 is a plan view and a sectional view of an IC to which the light shielding measures of the present invention are applied. In Figure 1, 8 is an IC chip, 9 is a pound pad, 12.18
is the first metal wiring layer, 11.16 is the second metal wiring layer, 10.14 is the third metal wiring layer, and 15.
17 is an insulating layer between metal wiring layers. As can be seen from Fig. 2(a), the metal wiring in each layer is not linear like the conventional wiring shown in Fig.
4] is constructed so as to spread as much as possible within the filter layer to cover the layer. By doing this, if a multilayer wiring structure is formed, the gaps created in each layer will be filled with metal wiring in other layers, and light will be completely blocked. That is, in the embodiment shown in FIG. 2(b), light is shielded by at least one of the metal interconnections in the first layer, second layer, and third layer.

金属配線幅を広げることによる浮遊容量の増加は大線幅
の配線の下には小線幅の配線を位置することにより防ぐ
ことができる。また線幅を広げることによるＩＣ集積度
の低下は多層配線化によって補償することができる。An increase in stray capacitance due to widening the metal wiring width can be prevented by placing a narrow line width wiring under a large line width wiring. Further, the reduction in IC integration density due to widening the line width can be compensated for by multilayer wiring.

以上のべた通り本発明は、金属配線の形状及び配置を改
良し、多層配線構造とすることによって、半導体装置の
電気的特性に悪影響を与える光を防ぐと（・う効果を有
するものである。As described above, the present invention has the effect of preventing light that adversely affects the electrical characteristics of a semiconductor device by improving the shape and arrangement of metal wiring and creating a multilayer wiring structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は従来のＩＣ配線を示す平面図、第１図（
ｂ）は従来のＩＣ配線を示す断面図、第２図（、）は本
発明によるＩＣ配線を示す平面図、第２図（ｂ）は本発
明によるＩＣ配線を示す断面図である。 １．８−ＩＣチップ、２，９・・・ポンディングパッド
、３．７．１９・・・光に敏感な素子領域、４．６．１
０．１１．１２．１４，１６．１８・・・金属配線層５
．１３・・・保護膜、１５．１７・・・金属配線層間絶
縁層。 第１図 （ｂ） 第２図 （ｂ）Figure 1(a) is a plan view showing conventional IC wiring;
FIG. 2(b) is a sectional view showing the conventional IC wiring, FIG. 2(,) is a plan view showing the IC wiring according to the present invention, and FIG. 2(b) is a sectional view showing the IC wiring according to the present invention. 1.8-IC chip, 2,9... bonding pad, 3.7.19... light sensitive element area, 4.6.1
0.11.12.14, 16.18...Metal wiring layer 5
．． 13... Protective film, 15.17... Metal wiring interlayer insulating layer. Figure 1 (b) Figure 2 (b)

Claims (1)

【特許請求の範囲】[Claims] 光に対して敏感に特性が変化する半導体装置において、
金属配線層と絶縁層からなる多層配線構造からなり、前
記半導体装置に入射する光を遮へいするごとく前記金属
配線層を拡巾して配置することにより、配線を遮光膜を
兼ねるごとく形成したことを特徴とする半導体装置。In semiconductor devices whose characteristics change sensitively to light,
The semiconductor device has a multilayer wiring structure consisting of a metal wiring layer and an insulating layer, and the metal wiring layer is widened and arranged so as to block light entering the semiconductor device, so that the wiring is formed so as to double as a light shielding film. Characteristic semiconductor devices.
JP57061303A 1982-04-13 1982-04-13 Semiconductor device Pending JPS58222546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57061303A JPS58222546A (en) 1982-04-13 1982-04-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57061303A JPS58222546A (en) 1982-04-13 1982-04-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58222546A true JPS58222546A (en) 1983-12-24

Family

ID=13167276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57061303A Pending JPS58222546A (en) 1982-04-13 1982-04-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58222546A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687298A (en) * 1984-04-11 1987-08-18 Hosiden Electronics, Ltd. Forming an opaque metal layer in a liquid crystal display
US4910579A (en) * 1986-09-26 1990-03-20 International Business Machines Corporation Semiconductor integrated display device with overlapping electrodes
US4948231A (en) * 1984-04-09 1990-08-14 Hosiden Electronics Co. Ltd. Liquid crystal display device and method of manufacturing the same
US4963503A (en) * 1984-04-09 1990-10-16 Hosiden Electronics Co., Ltd. Method of manufacturing liquid crystal display device
US5597736A (en) * 1992-08-11 1997-01-28 Texas Instruments Incorporated High-yield spatial light modulator with light blocking layer
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948231A (en) * 1984-04-09 1990-08-14 Hosiden Electronics Co. Ltd. Liquid crystal display device and method of manufacturing the same
US4963503A (en) * 1984-04-09 1990-10-16 Hosiden Electronics Co., Ltd. Method of manufacturing liquid crystal display device
US4687298A (en) * 1984-04-11 1987-08-18 Hosiden Electronics, Ltd. Forming an opaque metal layer in a liquid crystal display
US4910579A (en) * 1986-09-26 1990-03-20 International Business Machines Corporation Semiconductor integrated display device with overlapping electrodes
US5597736A (en) * 1992-08-11 1997-01-28 Texas Instruments Incorporated High-yield spatial light modulator with light blocking layer
US5818095A (en) * 1992-08-11 1998-10-06 Texas Instruments Incorporated High-yield spatial light modulator with light blocking layer
CN1041019C (en) * 1992-08-11 1998-12-02 德克萨斯仪器股份有限公司 High-yield spatial light modulator with light blocking layer
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors
US8999764B2 (en) * 2007-08-10 2015-04-07 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors
US10784200B2 (en) 2007-08-10 2020-09-22 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors

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