JPS6239820B2 - - Google Patents
Info
- Publication number
- JPS6239820B2 JPS6239820B2 JP55064310A JP6431080A JPS6239820B2 JP S6239820 B2 JPS6239820 B2 JP S6239820B2 JP 55064310 A JP55064310 A JP 55064310A JP 6431080 A JP6431080 A JP 6431080A JP S6239820 B2 JPS6239820 B2 JP S6239820B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor element
- contact area
- contact
- alpha rays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 66
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000005260 alpha ray Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
この発明はα線によるソフトエラーを防止する
ことができる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can prevent soft errors caused by alpha rays.
通常、半導体集積回路装置はシリコンなどの半
導体基板の表面付近にトランジスタ、ダイオー
ド、抵抗、コンデンサなどの電気部品を作り込
み、アルミニウムなどの導電体結線により半導体
回路を形成し、この半導体素子をセラミツクなど
で作つたパツケージに融着し、アルミニウムなど
の金属細線によりチツプ上のボンデイングパツド
とパツケージのリード間を接続し、蓋を被せて製
造するものである。一方、前記構造の半導体装置
では近年セラミツクパツケージなどから放射され
るα線によつて、半導体集積回路装置が誤動作す
る、いわゆるソフトエラーの問題がクローズアツ
プされてきた。これはパツケージの材料であるセ
ラミツクのみならず、金属蓋または蓋の溶接材な
どからも放射されるα線が半導体素子表面に入射
し、半導体基板中に電子・正孔対を発生させ、こ
のキヤリアによつて半導体集積回路装置が誤動作
する欠点があつた。 Normally, a semiconductor integrated circuit device has electrical components such as transistors, diodes, resistors, and capacitors built near the surface of a semiconductor substrate made of silicon, etc., a semiconductor circuit is formed by connecting conductors such as aluminum, and this semiconductor element is made of ceramic or other materials. The bonding pads on the chip are connected to the leads of the package using thin metal wires such as aluminum, and the leads of the package are covered with a lid. On the other hand, in semiconductor devices having the above-mentioned structure, the problem of so-called soft errors, in which semiconductor integrated circuit devices malfunction due to alpha rays emitted from ceramic packages, etc., has recently come to the fore. This is because alpha rays emitted not only from the ceramic material of the package, but also from the metal lid or the welding material of the lid, enter the surface of the semiconductor element, generate electron-hole pairs in the semiconductor substrate, and this carrier This has the disadvantage that the semiconductor integrated circuit device malfunctions.
したがつて、この発明の目的はα線を遮断し
て、ソフトエラーを防止することができると共
に、高集積度を実現できる半導体装置を提供する
ものである。 Therefore, an object of the present invention is to provide a semiconductor device that can block alpha rays, prevent soft errors, and realize a high degree of integration.
このような目的を達成するため、この発明は、
周辺部にボンデイングバツドを形成しかつこれよ
り内方へ複数の第１の接点領域を形成すると共に
少くとも各第１の接点領域により包囲される範囲
へ半導体回路を形成した第１の半導体素子と、各
第１の接点領域と対向する複数の第２の接点領域
を形成しかつ同一面へ半導体回路を形成すると共
にα線の透過しない厚さを有する第２の半導体素
子とを備え、第１の半導体素子に形成した各第１
の接点領域と第２の半導体素子に形成した各第２
の接点領域とを接続部材を介し対向して結合した
ものであり、以下実施例を用いて詳細に説明す
る。 In order to achieve this purpose, this invention
A first semiconductor element having a bonding pad formed in a peripheral portion, a plurality of first contact regions formed inwardly from the bonding pad, and a semiconductor circuit formed in at least an area surrounded by each first contact region. and a second semiconductor element forming a plurality of second contact regions facing each of the first contact regions, forming a semiconductor circuit on the same surface, and having a thickness that does not transmit alpha rays. Each first semiconductor element formed on one semiconductor element
and each second contact region formed on the second semiconductor element.
The contact area of the contact area is coupled to face each other via a connecting member, and will be described in detail below using examples.
第１図はこの発明に係る半導体装置の一実施例
を示す平面図であり、第２図は第１図のＡ−
A′断面図である。同図において、１は半導体回
路を含む第１の半導体素子、２はこの第１の半導
体素子１の周辺部に設けた複数個のボンデイング
パツド、３はそれぞれのボンデイングパツド２に
接続する金属細線、４は第１の半導体素子１の周
辺部より内方に形成した第１の接点領域、５は半
導体素子支持台、６はα線が透過しない厚さを有
する第２の半導体素子、７はこの第２の半導体素
子６に第１の接点領域４と対向して形成した第２
の接点領域、８は前記第１の接点領域４と第２の
接点領域７とを接続するハンダ球からなる接続部
材である。 FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, and FIG.
It is an A′ cross-sectional view. In the figure, 1 is a first semiconductor element including a semiconductor circuit, 2 is a plurality of bonding pads provided around the first semiconductor element 1, and 3 is a metal connected to each bonding pad 2. 4 is a first contact region formed inward from the peripheral portion of the first semiconductor element 1; 5 is a semiconductor element support; 6 is a second semiconductor element having a thickness that does not allow alpha rays to pass through; 7; is a second semiconductor element 6 formed opposite to the first contact region 4.
The contact area 8 is a connecting member made of a solder ball that connects the first contact area 4 and the second contact area 7.
なお、第２の半導体素子６の厚さは前記のよう
にα線が透過しない厚さをもつことが必要である
が、通常α線は5MeV程度のエネルギーであり、
シリコン中をせいぜい25〜30μｍまでしか進入し
得ないので、これ以上の厚さがあればα線の透過
を防止することができ、通常は200μｍ以上ある
ため、十分である。 Note that the second semiconductor element 6 needs to have a thickness that does not allow α-rays to pass through, as described above, but normally α-rays have an energy of about 5 MeV,
Since it is possible to penetrate silicon only up to a thickness of 25 to 30 μm at most, a thickness greater than this can prevent alpha rays from passing through, and usually 200 μm or more is sufficient.
また、第１の半導体素子１には、少くとも第１
の接点領域４により包囲される範囲内に半導体回
路が形成されており、第２の半導体素子６には、
第２の接点領域７と同一面に同様の半導体回路が
形成されている。 Further, the first semiconductor element 1 includes at least a first
A semiconductor circuit is formed within the range surrounded by the contact area 4, and the second semiconductor element 6 includes:
A similar semiconductor circuit is formed on the same surface as the second contact area 7.
次に、上記構成に係る半導体装置の製作につい
て説明する。 Next, manufacturing of the semiconductor device having the above configuration will be explained.
まず、第１の半導体素子１および第２の半導体
素子６を別々に公知の方法によつて形成する。そ
して、第１の半導体素子１の周辺部に複数個のボ
ンデイングバツド２を形成し、かつ、これより内
方へ第１の接点領域４および半導体回路を形成す
るが、この第１の接点領域４はニツケル、銅メツ
キによつて形成する。一方、第２の半導体素子６
上には第２の接点領域７および半導体回路を形成
したのち、ハンダ球からなる接続部材８を設ける
が、この第２の接点領域７は例えばアルミニウム
上にニツケル、銅をメツキした通常の配線用メタ
ル材料で形成する。つぎに、この第２の半導体素
子６を裏返しにして、第１の接点領域４と第２の
接点領域７とを接続部材８を介し互に対向して配
置する。ついで、N2ガス雰囲気300℃で熱処理を
行なうことによつて、第１の接点領域４と第２の
接点領域７を接続部材８によつて接続することが
できる。このように、第１の半導体素子１と第２
の半導体素子６とを結合して構成した複合半導体
素子をパツケージの半導体素子支持台５に融着す
る。そして、金属細線３の一端をボンデイングパ
ツド２に接続すると共に金属細線３の他端をパツ
ケージの図示せぬリード線に接続する。 First, the first semiconductor element 1 and the second semiconductor element 6 are formed separately by a known method. Then, a plurality of bonding pads 2 are formed around the periphery of the first semiconductor element 1, and a first contact region 4 and a semiconductor circuit are formed inwardly from the bonding pads 2. 4 is formed by nickel and copper plating. On the other hand, the second semiconductor element 6
After forming a second contact area 7 and a semiconductor circuit thereon, a connecting member 8 made of a solder ball is provided, but this second contact area 7 is made of, for example, an ordinary wiring layer made of nickel or copper plated on aluminum. Made of metal material. Next, this second semiconductor element 6 is turned over, and the first contact area 4 and the second contact area 7 are placed facing each other with the connection member 8 in between. Next, the first contact region 4 and the second contact region 7 can be connected by the connecting member 8 by performing heat treatment at 300° C. in an N 2 gas atmosphere. In this way, the first semiconductor element 1 and the second
The composite semiconductor device formed by combining the semiconductor devices 6 and 6 is fused to the semiconductor device support base 5 of the package. Then, one end of the thin metal wire 3 is connected to the bonding pad 2, and the other end of the thin metal wire 3 is connected to a lead wire (not shown) of the package.
このように構成した半導体素子においてはパツ
ケージまたは蓋などから放射されるα線は第２の
半導体素子６によつて遮蔽されるため、ソフトエ
ラーを防止することができる。しかも、第１の半
導体素子１と第２の半導体素子６との間の間隔が
小さいため、横方向から入射するα線を無視する
ことができる。たゞし第１の半導体素子１のワイ
ヤボンデイングパツド２付近は金属細線３があれ
ため、露出されており、α線に曝されているが、
α線に当つても誤動作しない回路であねばソフト
エラーは発生しないことはもちろんである。この
ため、α線が問題になる集積回路装置は例えば
MOSダイナミツクメモリのメモリ部などに限定
されており、第２の半導体素子６によりカバーさ
れる範囲へこれらを形成し、この範囲のみを遮蔽
すれば実際上問題はない。また、第２の半導体素
子６は前記したように、α線が透過しない程度の
厚さがあればよいことはもちろんであるが、更に
強力な放射線に曝される場合には、裏面に例えば
Au、Pt、Ta、Ｗなどの放射線を遮断する被膜を
形成すればよい。 In the semiconductor device configured in this manner, α rays emitted from the package or the lid are blocked by the second semiconductor device 6, so that soft errors can be prevented. Moreover, since the distance between the first semiconductor element 1 and the second semiconductor element 6 is small, α rays incident from the lateral direction can be ignored. However, the vicinity of the wire bonding pad 2 of the first semiconductor element 1 is exposed due to the thin metal wire 3 and is exposed to alpha rays.
Of course, soft errors will not occur if the circuit does not malfunction even when exposed to alpha rays. For this reason, integrated circuit devices where alpha rays are a problem are, for example,
This is limited to the memory part of a MOS dynamic memory, and there is no problem in practice if these are formed in the range covered by the second semiconductor element 6 and only this range is shielded. Further, as described above, the second semiconductor element 6 need only have a thickness that does not allow alpha rays to pass through, but if it is exposed to more intense radiation, the back surface may be
A radiation blocking film such as Au, Pt, Ta, W, etc. may be formed.
したがつて、第２の半導体素子６の付加によ
り、高集積度が実現すると共にLSIでは半導体素
子の集積規模が増大するのに従い、いわゆる欠陥
による歩留りが低下するが、各機能を複数に分割
し、各個に製造することによつて、大幅に歩留り
の向上を図ることができるので、このような観点
からも歩留りを向上させ、コストの低下を図るこ
とができる。 Therefore, by adding the second semiconductor element 6, a high degree of integration is achieved, and as the scale of integration of semiconductor elements increases in LSI, the yield due to so-called defects decreases. By manufacturing each of them individually, it is possible to significantly improve the yield, so from this point of view as well, the yield can be improved and the cost can be reduced.
以上、詳細に説明したように、この発明に係る
半導体装置によれば簡単な構造により、α線を遮
断することができるのと共に、高集積度が実現
し、ソフトエラーの防止およびLSIの小形化、高
機能化が同時に得られる効果を呈する。 As described above in detail, the semiconductor device according to the present invention has a simple structure that can block alpha rays, achieve high integration, prevent soft errors, and reduce the size of LSI. , exhibits the effect of achieving high functionality at the same time.
第１図はこの発明に係る半導体装置の一実施例
を示す平面図、第２図は第１図のＡ−A′断面図
である。
１…第１の半導体素子、２…ボンデイングパツ
ド、３…金属細線、４…第１の接点領域、５…半
導体素子支持台、６…第２の半導体素子、７…第
２の接点領域、８…接続部材。なお、図中、同一
要素は同一または相当部分を示す。
FIG. 1 is a plan view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view taken along line A-A' in FIG. DESCRIPTION OF SYMBOLS 1... First semiconductor element, 2... Bonding pad, 3... Metal thin wire, 4... First contact area, 5... Semiconductor element support base, 6... Second semiconductor element, 7... Second contact area, 8... Connection member. In addition, in the figures, the same elements indicate the same or equivalent parts.
Claims (1)
れより内方へ複数の第１の接点領域を形成すると
共に少くとも前記各第１の接点領域により包囲さ
れる範囲へ半導体回路を形成した第１の半導体素
子と、前記第１の接点領域と対向する複数の第２
の接点領域を形成しかつ同一面へ半導体回路を形
成すると共にα線の透過しない厚さを有する第２
の半導体素子とを備え、前記第１の半導体素子に
形成した各第１の接点領域と第２の半導体素子に
形成した各第２の接点領域とを接続部材を介し対
向して結合したことを特徴とする半導体装置。 ２ 前記第２の半導体素子の接点領域を形成しな
い面にα線の遮蔽被膜を形成したことを特徴とす
る特許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A bonding pad is formed in a peripheral portion, and a plurality of first contact regions are formed inwardly from the bonding pad, and a semiconductor circuit is formed at least in an area surrounded by each of the first contact regions. a plurality of second semiconductor elements facing the first contact region;
A second contact area is formed, a semiconductor circuit is formed on the same surface, and the thickness is such that alpha rays do not pass through.
a semiconductor element, and each first contact area formed on the first semiconductor element and each second contact area formed on the second semiconductor element are coupled to face each other via a connecting member. Characteristic semiconductor devices. 2. The semiconductor device according to claim 1, wherein an α-ray shielding film is formed on a surface of the second semiconductor element on which a contact region is not formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6431080A JPS56158467A (en) | 1980-05-12 | 1980-05-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6431080A JPS56158467A (en) | 1980-05-12 | 1980-05-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56158467A JPS56158467A (en) | 1981-12-07 |
| JPS6239820B2 true JPS6239820B2 (en) | 1987-08-25 |
Family
ID=13254530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6431080A Granted JPS56158467A (en) | 1980-05-12 | 1980-05-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56158467A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988864A (en) * | 1982-11-12 | 1984-05-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US6682954B1 (en) | 1996-05-29 | 2004-01-27 | Micron Technology, Inc. | Method for employing piggyback multiple die #3 |
| US6208018B1 (en) | 1997-05-29 | 2001-03-27 | Micron Technology, Inc. | Piggyback multiple dice assembly |
| US6900528B2 (en) | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51102566A (en) * | 1975-03-07 | 1976-09-10 | Suwa Seikosha Kk | Shusekikairo |
| JPS5339068A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Semiconductor device |
| JPS5365063A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Semiconductor device |
| JPS5552246A (en) * | 1978-10-13 | 1980-04-16 | Mitsubishi Electric Corp | Semiconductor device |
-
1980
- 1980-05-12 JP JP6431080A patent/JPS56158467A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51102566A (en) * | 1975-03-07 | 1976-09-10 | Suwa Seikosha Kk | Shusekikairo |
| JPS5339068A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Semiconductor device |
| JPS5365063A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Semiconductor device |
| JPS5552246A (en) * | 1978-10-13 | 1980-04-16 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56158467A (en) | 1981-12-07 |
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