JPS5854661A - Multilayer ceramic semiconductor package - Google Patents

Multilayer ceramic semiconductor package

Info

Publication number
JPS5854661A
JPS5854661A JP56152882A JP15288281A JPS5854661A JP S5854661 A JPS5854661 A JP S5854661A JP 56152882 A JP56152882 A JP 56152882A JP 15288281 A JP15288281 A JP 15288281A JP S5854661 A JPS5854661 A JP S5854661A
Authority
JP
Japan
Prior art keywords
semiconductor package
signal lines
multilayer ceramic
ground
crosstalk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56152882A
Other languages
Japanese (ja)
Inventor
Mitsuhisa Shimizu
光久 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56152882A priority Critical patent/JPS5854661A/en
Publication of JPS5854661A publication Critical patent/JPS5854661A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent the production of a crosstalk by shielding signal lines of a multilayer ceramic semiconductor package and arranging them in different steps. CONSTITUTION:An integrated circuit chip 4 is arranged on a ground or a power source line 1, and is connected via wirings 5 to signal lines 2. The lines 2 are insulated via ceramics 3 at the respective layers, are shielded with the ground or the power source line, and the signal lines are arranged in different steps. Thus, the crosstalk and noise between the lines can be prevented. Since it is not necessary to increase the thickness of the ceramic layer, it is not necessary to lower the integration.

Description

【発明の詳細な説明】 本発明は多層セラくツク半導体パッケージに係り、さら
に詳しく述べるならば信号ラインにシールド’ｋＡ備せ
しめた多層セラ＜　ＩＦり半導体パッケージに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer ceramic semiconductor package, and more specifically, to a multilayer ceramic semiconductor package in which a signal line is provided with a shield 'kA'.

Ｌ８Ｉ（大規模集積回路）の高性能化、高集積化が進み
、端子数が増加する一方で半導体パッケージは縮小化さ
れる傾向にある。この半導体パッケージの縮小化に伴な
い多層セランツクパッケージが使用されているが、パッ
ケージ内に配設され九傷号ライン間の距離が短くなりク
ロストーク等の電気的特性の不具合倉生ずる。As the performance and integration of L8I (Large Scale Integrated Circuits) progresses, the number of terminals increases, while semiconductor packages tend to become smaller. With the miniaturization of semiconductor packages, multi-layer cellulose packages are being used, but the distance between the nine fault lines disposed within the package becomes short, resulting in defects in electrical characteristics such as crosstalk.

すなわち従来は、第１図及び第２図に示したような多層
セラ＜　ツクパッケージではグランド又は電源ライン１
上に集積回路チップ４が配設されており、蚊チップ４は
ワイヤ５によって信号ライン２と接続されている。第１
図の一部側面図である第２図で示されるように信号ライ
ン２が平行に走り且つセラミック３に組込まれた多層構
造ｔしている。しかしながら、帥述のように回路の高性
能高積化に伴なって信号ライン２間の距離りがより接近
することになり、信号ライン間の寄生容量等にエリクロ
ストーク（漏話）が発生する６％にこのクロストークは
信号ライン間の距離りが短い場合の他に、配線パターン
が長く平行する場合がより問題となる。又、信号ライン
間の距離が短く、且つ配線が長い場合にはノイズが混入
し、半導体素子の電気的特性に不利な影響を与える。In other words, conventionally, in multilayer ceramic packages as shown in Figs. 1 and 2, the ground or power line 1
An integrated circuit chip 4 is arranged on top, and the mosquito chip 4 is connected to the signal line 2 by a wire 5. 1st
As shown in FIG. 2, which is a partial side view of the figure, the signal lines 2 run in parallel and are incorporated into the ceramic 3 in a multilayer structure. However, as mentioned above, as the high performance and high integration of circuits increases, the distance between the two signal lines becomes closer, and Eric crosstalk (crosstalk) occurs due to the parasitic capacitance between the signal lines. 6%, this crosstalk becomes a problem not only when the distance between signal lines is short, but also when the wiring patterns are long and parallel. Furthermore, if the distance between the signal lines is short and the wiring is long, noise will be mixed in, which will adversely affect the electrical characteristics of the semiconductor element.

そこで本発明に上記欠点全解消して信号ライン間でのク
ロストーク等のない良好な多層セラミッり半導体パッケ
ージ會提供するととｔ目的とすゐ。Therefore, it is an object of the present invention to eliminate all of the above-mentioned drawbacks and provide an excellent multilayer ceramic semiconductor package free of crosstalk between signal lines.

本発明の目的は複数の信号ラインが多層に配置すしてい
る半導体パッケージにおいて各信号ラインがグランド又
は電源ラインでシールドされており、且つ段違いに配置
されていること’ｒ＊＊とする半導体パッケージによっ
て達成される。An object of the present invention is to provide a semiconductor package in which a plurality of signal lines are arranged in multiple layers, in which each signal line is shielded by a ground or power supply line, and is arranged at different levels. achieved.

ルドし、更に鋏傷号うイン會平行に配設せずに段違いに
配設して信号間の距離留出来る限り近接せしめないよう
にすゐことを特徴としている。In addition, the scissor signals are not arranged parallel to each other, but are arranged at different levels, so that the distance between the signals is kept as close as possible so that they do not come close to each other.

以下本発明を実施例に基づいて詳細に説明する。The present invention will be described in detail below based on examples.

ｔ！５３図及び第４図は本発明に係る一つの実施例を説
明するための説明図である。T! FIG. 53 and FIG. 4 are explanatory diagrams for explaining one embodiment of the present invention.

第３図によればグランド又ｒｉｏｌｌ　Ｉ上圧乗積回路
チップ４逅配設されており、該集積回路チップ４はワイ
ヤ５によって信号ライン２に１続されて１ン６によって
シールドせしめられており、且つ各々の信号ライン２Ｆ
ｉ平行に配設されておらず段違いに配設されている。更
に又、本発明では信号ライン２は多層に配設されセラば
ツク３により各層毎に絶縁されている。このように本発
明によれば各信号ライン２．がグランド又は電源ライン
でシールドされており、しかも段違いに配設されている
友めに各信号ライン間がシールドされクロストークやノ
イズ等の発生が起こりにくくなる。金体セラ４　ｆり層
の厚さは従来の厚さ會維持することが出来、集積度の点
でも特に不利にならない半導体パッグージ管得ることが
出来る。As shown in FIG. 3, a voltage multiplier circuit chip 4 is disposed on the ground or Rioll I, and the integrated circuit chip 4 is connected to the signal line 2 by a wire 5 and shielded by a 1 line 6. , and each signal line 2F
i They are not arranged in parallel but at different levels. Furthermore, in the present invention, the signal line 2 is arranged in multiple layers, and each layer is insulated by a ceramic pack 3. Thus, according to the present invention, each signal line 2. are shielded by a ground or power supply line, and since they are arranged at different levels, each signal line is shielded, making crosstalk and noise less likely to occur. The thickness of the gold body ceramic 4 f layer can be maintained at the conventional thickness, and a semiconductor package tube can be obtained that is not particularly disadvantageous in terms of the degree of integration.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来の実施例を説明するための説明図
であり、ｔａｓ図、第４図は本発明に係る実施例を説明
するための一つの５Ｊ！施例を示す説明図でＴｏゐ。 １ｅＯ＠　グランド又は電源う１ン、　　２・・・・信
号ライン、　　３・・＠−セライ、り、　　４・１１集
積回路チップ、　　５００ワイヤ、　　６・・・・グラ
ンド電源ライン。FIG. 1 and FIG. 2 are explanatory diagrams for explaining a conventional embodiment, and TAS diagram and FIG. 4 are one 5J! diagram for explaining an embodiment according to the present invention. This is an explanatory diagram showing an example. 1eO@Ground or power supply line, 2...Signal line, 3...@-Serai, 4.11 integrated circuit chip, 500 wires, 6...Ground power line.

Claims (1)

【特許請求の範囲】[Claims] 複数の信号ラインが多層に配置されている多層上ライツ
ク半導体パッケージにおいて、帥配信号ラインの各々が
グランド又は電源ラインでシールドされており、且つ段
違いに配設されていることを特徴とする多層セライック
半導体パッケージ。In a multilayer top-light semiconductor package in which a plurality of signal lines are arranged in multiple layers, each of the main signal lines is shielded by a ground or power supply line, and is arranged at different levels. semiconductor package.
JP56152882A 1981-09-29 1981-09-29 Multilayer ceramic semiconductor package Pending JPS5854661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56152882A JPS5854661A (en) 1981-09-29 1981-09-29 Multilayer ceramic semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56152882A JPS5854661A (en) 1981-09-29 1981-09-29 Multilayer ceramic semiconductor package

Publications (1)

Publication Number Publication Date
JPS5854661A true JPS5854661A (en) 1983-03-31

Family

ID=15550177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56152882A Pending JPS5854661A (en) 1981-09-29 1981-09-29 Multilayer ceramic semiconductor package

Country Status (1)

Country Link
JP (1) JPS5854661A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2573272A1 (en) * 1984-11-14 1986-05-16 Int Standard Electric Corp PROCESS FOR PRODUCING A SUBSTRATE COMPRISING A COAXIAL CONDUCTOR
JPS6294315A (en) * 1985-10-21 1987-04-30 Yoshino Kogyosho Co Ltd Forming of liner in cap
JPS62119807A (en) * 1984-11-14 1987-06-01 インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン Conductor and its manufacture
JPS62219691A (en) * 1986-03-20 1987-09-26 富士通株式会社 Thick film hybrid integrated circuit
JPS62259500A (en) * 1986-05-02 1987-11-11 株式会社東芝 Circuit board
JPS6393672U (en) * 1986-12-10 1988-06-17
JPH01227492A (en) * 1988-03-07 1989-09-11 Shinko Electric Ind Co Ltd Substrate for electronic components
US4881116A (en) * 1986-06-02 1989-11-14 Fujitsu Limited Package for integrated circuit
JPH06169107A (en) * 1991-02-19 1994-06-14 American Teleph & Telegr Co <Att> Optical package
JPH07501910A (en) * 1992-09-24 1995-02-23 ヒューズ・エアクラフト・カンパニー Multilayer three-dimensional structure with internal ferromagnetic vias
EP1577945A3 (en) * 2004-02-04 2007-11-28 International Business Machines Corporation Module power distribution network
CN107995776A (en) * 2017-12-14 2018-05-04 武汉电信器件有限公司 A kind of circuit board and crosstalk eliminating method for being used to shield crosstalk

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2573272A1 (en) * 1984-11-14 1986-05-16 Int Standard Electric Corp PROCESS FOR PRODUCING A SUBSTRATE COMPRISING A COAXIAL CONDUCTOR
JPS62119807A (en) * 1984-11-14 1987-06-01 インタ−ナシヨナル・スタンダ−ド・エレクトリツク・コ−ポレイシヨン Conductor and its manufacture
JPS6294315A (en) * 1985-10-21 1987-04-30 Yoshino Kogyosho Co Ltd Forming of liner in cap
JPS62219691A (en) * 1986-03-20 1987-09-26 富士通株式会社 Thick film hybrid integrated circuit
JPS62259500A (en) * 1986-05-02 1987-11-11 株式会社東芝 Circuit board
US4881116A (en) * 1986-06-02 1989-11-14 Fujitsu Limited Package for integrated circuit
JPS6393672U (en) * 1986-12-10 1988-06-17
JPH01227492A (en) * 1988-03-07 1989-09-11 Shinko Electric Ind Co Ltd Substrate for electronic components
JPH06169107A (en) * 1991-02-19 1994-06-14 American Teleph & Telegr Co <Att> Optical package
JPH07501910A (en) * 1992-09-24 1995-02-23 ヒューズ・エアクラフト・カンパニー Multilayer three-dimensional structure with internal ferromagnetic vias
EP1577945A3 (en) * 2004-02-04 2007-11-28 International Business Machines Corporation Module power distribution network
CN107995776A (en) * 2017-12-14 2018-05-04 武汉电信器件有限公司 A kind of circuit board and crosstalk eliminating method for being used to shield crosstalk

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