JPS5972152A - Master slice type integrated circuit - Google Patents

Abstract

PURPOSE:To shunt a high-frequency component overlapping to a power supply, and to relax supply noises by forming a plurality of supply wirings for feeding the power supply and a plurality of supply wirings feeding potential different from said wirings to each of circuit units constituting an IC while they are crossed at right angles with mutually different layers and setting capacitors up to these crossed sections. CONSTITUTION:One cell Aij is constituted of a region surrounded by a chain line and the cells are arranged on a chip in a matrix shape, the power supply is extended up to a pectinate electrode wiring 6 shown in a solid line and a pectinate electrode wiring 7 shown in a broken line from pads 4 and 5, and all cells are supplied with the power supply. The supply wirings 6 and 7 among them are mutually insulated previously by inter-layer insulating films, and each cell is supplied with power supplies at different potential. In the constitution, the capacitors are set up to all of the crossed sections of the wirings 6 and 7, the high-frequency components of supply noises are shunted into the chip, and the generation of the logic malfunction of the cells is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements to master slice integrated circuits, and more particularly to improvements in master slice integrated circuits.

In general, in semiconductor integrated circuits including master slice integrated circuits, high frequency noise (hereinafter referred to as
Power supply noise (hereinafter referred to as power supply noise) often causes logic malfunctions within semiconductor integrated circuit chips (hereinafter referred to as chips).

In order to prevent the above power supply noise, 1 For example, as shown in Figure 1, a capacitor Ce is inserted outside the semiconductor integrated circuit chip 1 between the power supply (for example, between the power terminal and the ground terminal of the power supply device that supplies power to the integrated circuit). However, measures are often taken to shunt the high-frequency components of power supply noise to suppress malfunctions inside the chip. Note that in FIG. 1, 2 and 3 are external wirings that should be connected to a power source. However, the above method does not provide a measure to prevent fluctuations in the power supply potential caused by the electrical operation of elements located at one location inside the chip from affecting elements located at other locations.

The present invention has been made to address the above-mentioned problems, and its object is to provide a one star slice type integrated circuit that is effective in alleviating power supply noise.

A master slice type integrated circuit according to the present invention.

In a master slice type integrated circuit in which a plurality of circuit units having all arbitrary logic functions are provided on one chip and each circuit unit is provided with a desired logic function by electrically connecting the circuit units, each of the circuit units is provided with a power supply. and a plurality of power supply wirings that supply each of the circuit units with a power supply having a different potential from that of the power supply wiring are provided in different layers in a direction orthogonal to each other, and the two types of power supply A master slice integrated circuit is characterized in that a capacitor is provided at the intersection of wires.

Hereinafter, the present invention will be explained in detail based on Examples.

An example shown in the accompanying drawings will be explained.

FIG. 2 is an explanatory diagram showing the structure of a master slice type integrated circuit according to the present invention. The region surrounded by a chain line in FIG. 2 constitutes one cell Alj, which is arranged in rows and columns on the chip. Power supplies extend from pads 4 and 5 to comb-like power supply wiring lines 6 (solid lines) and 7 (dashed lines), respectively, and are laid so that power is supplied to all cells on the chip. Here, it is assumed that the power supply wirings 6 and 7 are insulated from each other by an interlayer insulating film, and supply power at different potentials to each cell. The present invention aims to help prevent power supply noise by providing a capacitor at the intersection of power supply lines 6 and 7 in FIG. FIG. 3 is an enlarged view of FIG. 2 by ff1s, and the same reference numerals represent the same parts as in FIG. The shaded area 8 represents a capacitor section, and the capacitor has a sound effect that shunts high frequency components of power supply noise caused by the electrical operation of elements inside the chip to prevent logic malfunctions of the cells. That is, the capacitor plays the role of stabilizing the power supply potential inside the chip. In FIG. 3, the power supply line 7 is made slightly thicker at the intersection with the power supply line 6 in order to increase the capacitance of the capacitor.

Next, an example of the structure of a capacitor used in the present invention is shown in FIG. In FIG. 4, 9 is a semiconductor substrate, 10 is a silicon oxide film that insulates the semiconductor substrate 9 and the first wiring layer 11;
Reference numeral 12 denotes a silicon oxide film that insulates the first wiring layer 11 and the second wiring layer 13. Reference numeral 14 is a silicon oxide film which is patterned by ordinary photolithography and etched to a thickness of about 500λ.

Generally, in a master slice type integrated circuit, automatic cell placement and automatic wiring between cells are all performed by an automatic design system using a converter.

Therefore, in order to satisfy the reliability of the circuit for any automatic cell placement, a relatively wide power supply wiring width is required, so in the master slice integrated circuit with the configuration shown in The capacitance of the capacitor, such as the example shown in FIG. 4, can be relatively large.

As can be seen from the above description, according to the present invention, different types of power wiring of a master slice type integrated circuit are laid in mutually different layers in mutually orthogonal directions, and a capacitor is provided at the intersection of the different types of power supply wiring. Accordingly, it is possible to obtain a master slice type integrated circuit that shunts high frequency components superimposed on the power supply, and is therefore effective in alleviating power supply noise.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional mitigation method for power supply noise. Figure 2 is an explanatory diagram showing the configuration of a master slice integrated circuit according to the present invention. Figure 3 is a partially enlarged view of Figure 2. FIG. 4 shows a cross-sectional view of the Rel capacitor used in the present invention. 1... Semiconductor integrated circuit chip, 2.3. River...
External power wiring, 4, 5...Power pad, 6
．． 7...Power supply wiring, 8...Capacitor, 9...Semiconductor substrate, 10,12.14...
...Silicone oxide film, 11゜13...Power supply wiring, C...Capacitor sA"J...Cell. Fig. 7 Z 4 Atsushi Kasumi, 3 Fig. Atsushi?

Claims (1)

[Claims] In a master slice type integrated circuit which has a plurality of circuit units each having an arbitrary logic function on one chip and which has a desired logic function by electrically connecting the circuit units, the circuit unit A plurality of power supply wirings supplying power to each of the circuit units, and a plurality of power supply wirings supplying power of a potential different from that of the power supply wiring to each of the circuit units are provided in a direction perpendicular to different layers, and 2
A master slice type integrated circuit characterized by providing a capacitor at the intersection of different power supply wirings.