JPS62147746A - Integrated circuit structure - Google Patents
Integrated circuit structureInfo
- Publication number
- JPS62147746A JPS62147746A JP28883385A JP28883385A JPS62147746A JP S62147746 A JPS62147746 A JP S62147746A JP 28883385 A JP28883385 A JP 28883385A JP 28883385 A JP28883385 A JP 28883385A JP S62147746 A JPS62147746 A JP S62147746A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wafer
- groups
- circuit
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 7
- 230000002950 deficient Effects 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野〕
本発明は集積回路構造に関し、特に大規模論理横道を持
つシステムに使用される一ウェーハ集積回路構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to integrated circuit structures, and more particularly to single wafer integrated circuit structures used in systems with large scale logic paths.
従来、例えば大規模論理構造システムに使用される集積
回路構造として接続点を減少し信頼性を向上し、近接配
線が可能になり高速化、高密度。Conventionally, integrated circuit structures used, for example, in large-scale logic structure systems, reduce connection points, improve reliability, and enable close wiring, resulting in faster speeds and higher density.
小型化を達成する方式として−ウェーハで一集積回路を
構成するというアイディアは出されているがいまだ実用
に供されていない。As a method for achieving miniaturization, the idea of constructing a single integrated circuit using a wafer has been proposed, but it has not yet been put to practical use.
（発明が解決しようとする問題点：）
上述し、た従来の一ウェーハー集積回路という技術は、
−ウェーハ内に従来多数の集積回路チップとして構成し
た回路機能を一枚のウェーハに作り込んだものである。(Problem to be solved by the invention:) The conventional one-wafer integrated circuit technology described above is
-Circuit functions that were conventionally configured as multiple integrated circuit chips within a wafer are integrated into a single wafer.
従ってウェーハに内在する結晶欠陥の存在及び、集積回
路作り込みの段階での不具合の発生により、−ウェーハ
全体が良品になる確立が極めて低いという欠点があり、
実用が困難であった。Therefore, due to the presence of crystal defects inherent in the wafer and the occurrence of defects at the stage of fabricating integrated circuits, there is a drawback that the probability that the entire wafer will be a good product is extremely low.
It was difficult to put it into practical use.
本発明の目的は、従来の欠点を除去し、歩留りよく形成
でき、実用に供し得るーウェーハー集積回路の集積回路
構造を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit structure of a wafer integrated circuit which eliminates the conventional drawbacks, can be formed with high yield, and can be put to practical use.
本発明の集積回路構造は一枚のウェーハ内に、ウェーハ
上面から下面に貫通ずる穴を有し、該穴以外のウェーハ
内は外部端子をもつ独立した複数の集積回路群を有し、
前記穴部分には集積回路をはめ込んな一ウェーハ集積回
路群と、該−ウェーハ集積回路群の上面に形成した一ウ
ェーハ集積回路群中の各集積回路の外部端子同志を結ぶ
一層または多層の配線とを含んで構成される。The integrated circuit structure of the present invention has a hole penetrating from the upper surface to the lower surface of the wafer in one wafer, and the inside of the wafer other than the hole has a plurality of independent integrated circuit groups having external terminals,
A wafer integrated circuit group in which an integrated circuit is fitted into the hole portion, and a single-layer or multi-layer wiring connecting external terminals of each integrated circuit in the wafer integrated circuit group formed on the top surface of the wafer integrated circuit group. It consists of:
次に、本発明の実施例について図面を参照して説明する
。第１図（ａ）、（ｂ）乃至第３図（ａ＞、（ｂ）は、
本発明の一実施例の構造並びにその製造方法を説明する
なめに、工程順に示した平面図及びその断面図である。Next, embodiments of the present invention will be described with reference to the drawings. Figures 1 (a), (b) to 3 (a>, (b) are
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view and a cross-sectional view thereof shown in order of steps for explaining the structure and manufacturing method of an embodiment of the present invention.
まず、第１図（ａ＞、（ｂ）に示すように、つ工−ハ１
上に、上面に外部Ｊ１匈子３を有する集積回路群Ａ、Ｂ
、Ｃ，Ｄ、Ｅ、Ｆ、Ｇ、Ｈを形成し、各集積回路の特性
をチェ・ツクし良否を決める。本実施例ではその中で集
積回路りが不具合である為、集積回路り部分をウェーハ
１から切断し去った状態を示すもので、４はウェーハ上
面から下面に貫通する貫通穴である。なお、各集積回路
は独立した外部端子３が形成されている。また５は後の
工程で不良集積回路部分を除去するために予めダイシン
グソー等で形成した区画分離用溝である。First, as shown in Fig. 1 (a>, (b)),
on top, integrated circuit groups A and B having external J1 匈子 3 on the top surface;
, C, D, E, F, G, and H, and check the characteristics of each integrated circuit to determine whether it is acceptable or not. In this embodiment, the integrated circuit is defective, so the integrated circuit is cut off from the wafer 1. Reference numeral 4 designates a through hole penetrating from the upper surface to the lower surface of the wafer. Note that each integrated circuit has an independent external terminal 3 formed therein. Further, reference numeral 5 denotes a section separation groove formed in advance with a dicing saw or the like in order to remove a defective integrated circuit portion in a later process.
次に、第２図（ａ）、（ｂ）に示すように、ウェーハ１
の切断し去った集積回路り部分に集積回路Ｄ６をはめ込
む。ウェーハ１と集積回路Ｄ６の間は、導電性コンパウ
ンド７を充填し、固定する。Next, as shown in FIGS. 2(a) and (b), the wafer 1
The integrated circuit D6 is fitted into the integrated circuit portion that has been cut out. A conductive compound 7 is filled between the wafer 1 and the integrated circuit D6 and fixed.
次に、第３図（ａ＞、（ｂ）に示すように、第２図（ａ
）、（ｂ）にて示したーウェーハー集積回路群の上面に
、層間絶縁膜１１．第１層配線１３、第２層配線１４．
上下配線を結ぶスルーホール１２．引き出し線９．電源
バス１０．入出力バッド８が構成され、ウェーハ全体で
大規模回路を持つ集積回路を形成している。Next, as shown in FIG. 3(a>,(b)), as shown in FIG.
), (b) - An interlayer insulating film 11. First layer wiring 13, second layer wiring 14.
Through hole connecting upper and lower wiring 12. Lead line 9. Power bus10. Input/output pads 8 are configured to form an integrated circuit with a large scale circuit throughout the wafer.
以上説明したように本発明は、ウェーハ内に複数の集積
回路群を形成し、集積回路群のうち不具合が生じた集積
回路部分を、正常な集積回路と交換した後ウェーハ上面
に集積回路群を結ぶ配線を施す事により、−ウェーハ集
積回路を実現可能にできる効果がある。As explained above, the present invention forms a plurality of integrated circuit groups within a wafer, replaces a defective integrated circuit part of the integrated circuit group with a normal integrated circuit, and then replaces the integrated circuit group on the top surface of the wafer. Providing interconnecting wiring has the effect of making it possible to realize -wafer integrated circuits.
第１図（ａ＞、（ｂ）乃至第３図（ａ）、（ｂ）は本発
明の一実施例の構造並びに製造法を説明するなめに工程
順に示した平面図及び模式的断面図である。
１・・・ウェーハ、２・・・独立集積回路、３・・・独
立集積回路上の外部端子、４・・・貫通穴、５・・・区
画分離用溝、６・・・はめ込まれた集積回路Ｄ、７・・
・導電性コンパウンド、８・・・入出力パッド、９・・
・引き出し線、１０・・・電源バス、１１・・・層間絶
縁膜、１２・・・スルーホール、１３・・・第１層配線
、１４・・・第２層配線。
第 ／ 圀
＄ ３ 図Figures 1 (a>, (b) to 3 (a), (b) are plan views and schematic sectional views shown in the order of steps to explain the structure and manufacturing method of one embodiment of the present invention. 1...Wafer, 2...Independent integrated circuit, 3...External terminal on independent integrated circuit, 4...Through hole, 5...Groove for partition separation, 6...Inset Integrated circuit D, 7...
・Conductive compound, 8... Input/output pad, 9...
- Leading wire, 10... Power supply bus, 11... Interlayer insulating film, 12... Through hole, 13... First layer wiring, 14... Second layer wiring. No. / 圀＄3 fig.
Claims (1)
穴を有し、該穴以外のウェーハ内は外部端子をもつ独立
した複数の集積回路群を有し、前記穴部分には集積回路
をはめ込んだ一ウェーハ集積回路群と、該一ウェーハ集
積回路群の上面に形成した一ウェーハ集積回路群中の各
集積回路の外部端子同志を結ぶ一層または多層の配線と
を含むことを特徴とする集積回路構造。One wafer has a hole penetrating from the top surface to the bottom surface of the wafer, and the inside of the wafer other than the hole has a plurality of independent integrated circuit groups each having an external terminal, and the integrated circuit is fitted into the hole portion. 1. An integrated circuit comprising: a single wafer integrated circuit group; and single-layer or multilayer wiring connecting external terminals of each integrated circuit in the single wafer integrated circuit group formed on the top surface of the single wafer integrated circuit group. structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28883385A JPS62147746A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28883385A JPS62147746A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147746A true JPS62147746A (en) | 1987-07-01 |
Family
ID=17735336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28883385A Pending JPS62147746A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147746A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153700A (en) * | 1988-07-22 | 1992-10-06 | Nippondenso Co., Ltd. | Crystal-etched matching faces on semiconductor chip and supporting semiconductor substrate |
| US5208178A (en) * | 1990-08-02 | 1993-05-04 | Hitachi, Ltd. | Manufacturing a semiconductor integrated circuit device having on chip logic correction |
| US5909052A (en) * | 1986-03-12 | 1999-06-01 | Hitachi, Ltd. | Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane |
| US5968150A (en) * | 1986-03-12 | 1999-10-19 | Hitachi, Ltd. | Processor element having a plurality of CPUs for use in a multiple processor system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143435A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1985
- 1985-12-20 JP JP28883385A patent/JPS62147746A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6143435A (en) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909052A (en) * | 1986-03-12 | 1999-06-01 | Hitachi, Ltd. | Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane |
| US5968150A (en) * | 1986-03-12 | 1999-10-19 | Hitachi, Ltd. | Processor element having a plurality of CPUs for use in a multiple processor system |
| US6379998B1 (en) * | 1986-03-12 | 2002-04-30 | Hitachi, Ltd. | Semiconductor device and method for fabricating the same |
| US5153700A (en) * | 1988-07-22 | 1992-10-06 | Nippondenso Co., Ltd. | Crystal-etched matching faces on semiconductor chip and supporting semiconductor substrate |
| US5208178A (en) * | 1990-08-02 | 1993-05-04 | Hitachi, Ltd. | Manufacturing a semiconductor integrated circuit device having on chip logic correction |
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