JPS60160641A - Mounting of leadless package ic for board - Google Patents

Mounting of leadless package ic for board

Info

Publication number
JPS60160641A
JPS60160641A JP1739484A JP1739484A JPS60160641A JP S60160641 A JPS60160641 A JP S60160641A JP 1739484 A JP1739484 A JP 1739484A JP 1739484 A JP1739484 A JP 1739484A JP S60160641 A JPS60160641 A JP S60160641A
Authority
JP
Japan
Prior art keywords
leadless package
wiring
board
mounting
leadless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1739484A
Other languages
Japanese (ja)
Inventor
Koki Taniguchi
谷口　弘毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1739484A priority Critical patent/JPS60160641A/en
Publication of JPS60160641A publication Critical patent/JPS60160641A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To enable high density mounting and to contrive speedy treatment and improvement of performance due to the shortening of a signal line distance by mounting plural leadless package ICs each formed a required wiring on the side laminating in a longitudinal direction on a board. CONSTITUTION:Plural leadless package ICs 1 each formed with a required wiring 2 on the side are laminated in a longitudinal direction and mounted on a board 4 which has a wiring 5. The wiring 2 on the side is formed with conductive paste, etc. not only for the terminal required for such an integrated circuit as housed in the leadless package IC but also for the required signal line for a system. The laminated plural leadless package ICs are mutually connected with solder, etc. The leadless package IC has undercuts 31 and 32. The undercut 31 is used for separating the leadless package IC by an auxiliary tool, etc. if the leadless package IC has a defect and is required to be replaced. The undercut 32 can also prevent the shortening of an adjacent signal line.

Description

【発明の詳細な説明】 く技術分野〉 本発明はリードレスパッケージＩＣの基板実装方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for mounting a leadless package IC on a board.

〈従来技術〉 これ迄〜　ＩＣパッケージ等の電子部品を回路基板に実
装する方法として、一般に、平面的な実装が行われてい
る。平面実装は基板に電子部品を実装した場合、回路基
板上で占有面積を喰う欠点がある。また、配線が互いに
交差しないように両面Ｍ板を用い、多数のスルーホール
を設ける必要があり、又電子部品間の接続に余分な部品
を要し、製作が困難でコスト高となり、高密度実装には
限界があった。<Prior Art> Until now ~ Planar mounting is generally used as a method for mounting electronic components such as IC packages on circuit boards. Planar mounting has the disadvantage that when electronic components are mounted on a board, it takes up a lot of space on the circuit board. In addition, it is necessary to use a double-sided M board and provide many through holes to prevent wiring from crossing each other, and extra parts are required to connect electronic components, making manufacturing difficult and expensive, and high-density mounting. had its limits.

〈目　的〉 本発明は上記従来の欠点を除去するためになされたもの
で、側面に所望の配線（Ｉ　ＣＩＪ−上端子も含む）を
それぞれ形成した複数個のリードレスパッケージＩ　Ｃ
（ＬＳ　Ｉも含む）を縦方向に積層して基板に実装する
ことにより、高密度実装が可能であり、信号ライン距離
の短縮化によりスピード処理、性能向上が図れ、特にパ
スライン方式のＩＣ構成に適したリードレスパッケージ
ＩＣの基板実装方法を提供することを目的上する。また
、他の目的は、複数個のリードレスパッケージＩＣに切
込み部を設けることによりリードレスパッケージＩＣの
交換が容易であり、ＩＣ積層接続の際、隣接端子又は配
線間の短絡を阻止できるリードレスパッケージＩＣを提
供することである。<Purpose> The present invention has been made to eliminate the above-mentioned conventional drawbacks, and provides a plurality of leadless packages IC each having desired wiring (including an ICJ-upper terminal) formed on the side surface.
By stacking LSIs (including LSI) vertically and mounting them on the board, high-density mounting is possible, and by shortening the signal line distance, speed processing and performance can be improved, especially for pass line type IC configurations. The purpose of the present invention is to provide a method for mounting a leadless packaged IC on a board suitable for. Another purpose is to facilitate the replacement of leadless packaged ICs by providing notches in a plurality of leadless packaged ICs, and to prevent short circuits between adjacent terminals or wiring when stacking ICs. Our goal is to provide packaged ICs.

〈実施例〉 第１図において、１は側面に所望の配線２をそれぞれ形
成したリードレスパッケージＩＣ１を複数個（ＣＩ−Ｃ
４）縦方向に、配線５を有する基板４に積層して実装す
るようにしたものであり、側面の配線２としては、リー
ドレスパッケージＩＣに内蔵されている集積回路等に必
要な端子のみでなく、システムとして必要々信号線が導
体ペースト等により形成されている。積層された複数個
のり一ドレスパノケージＩＣは半田付等により相互間を
接続される。第２図は、リードレスパッケージＩＣの要
部詳細を示しており、切込み部３１と切込み部３２とを
有する。切込み部３１はリードレスパッケージＩＣに不
良品が発生し、交換が必要な場合、補助具等によりリー
ドレスパッケージＩＣを分離するために用いられる。ま
た、切込み部３２は隣接信号ラインの短縮を防止するこ
とができる。殊に、パスライン方式の構成の場合、−リ
ードレスパッケージＩＣの側面への配線も共通ラインが
多く一層効果的切ある。<Example> In FIG. 1, 1 is a plurality of leadless packages IC1 each having a desired wiring 2 formed on the side surface (CI-C
4) It is designed to be mounted by stacking it vertically on a substrate 4 having wiring 5, and the wiring 2 on the side is only the terminals necessary for the integrated circuit etc. built into the leadless package IC. However, the signal lines necessary for the system are formed of conductive paste or the like. A plurality of laminated glue-dressed panocage ICs are connected to each other by soldering or the like. FIG. 2 shows details of the main parts of the leadless package IC, which includes a notch 31 and a notch 32. As shown in FIG. The notch 31 is used to separate the leadless packaged IC with an auxiliary tool or the like when a defective leadless packaged IC occurs and needs to be replaced. Furthermore, the notch 32 can prevent adjacent signal lines from being shortened. In particular, in the case of a pass line type configuration, the wiring on the side surface of the leadless package IC has many common lines, making it even more effective.

第３図はリードレスパッケージＩＣの他の実施例を示し
、側面の配線２のみでなく、リードレスパッケージＩＣ
内部への配線２３を利用して配線の位置変更を行うこと
ができるようにしたものである。FIG. 3 shows another embodiment of the leadless package IC, in which not only the side wiring 2 but also the leadless package IC
The position of the wiring can be changed using the wiring 23 to the inside.

〈効　果〉 以上説明したように本発明によれば、側面に所望の配線
をそれぞれ形成した複数個のリードレスパッケージＩＣ
を縦方向に積層して基板に実装することにより、高密度
実装が可能であり、信号ライン距離の短縮化によりスピ
ード処理、性能向上が図れる。<Effects> As explained above, according to the present invention, a plurality of leadless package ICs each having desired wiring formed on the side surface
By stacking them vertically and mounting them on the board, high-density mounting is possible, and by shortening the signal line distance, speed processing and performance can be improved.

また、複数個のリードレスノくツケージＩＣに切込み部
を設ければ、パッケージＩＣの交換が容易であり〜ＩＣ
積層接続の際、隣接端子又は配線間の短絡を阻止できる
。In addition, if notches are provided in multiple leadless socket ICs, the package IC can be easily replaced.
During stacked connections, short circuits between adjacent terminals or wires can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるリードレスパッケージＩＣの基板
実装方法を示す要部組立斜視図、第２図はリードレスパ
ッケージＩＣの部分斜視図、第３図は他の実施例による
リードレスノきツケージＩＣの部分斜視図である。 符号の説明 １：リードレスパッケージＩＣ２：配線３．３１，３２
：切込み部　４；基板FIG. 1 is an assembled perspective view of a main part showing a method for mounting a leadless package IC on a board according to the present invention, FIG. 2 is a partial perspective view of a leadless package IC, and FIG. FIG. Explanation of symbols 1: Leadless package IC2: Wiring 3.31, 32
: Notch part 4; Substrate

Claims (1)

【特許請求の範囲】 １、側面に所望の配線をそれぞれ形成した複数個のリー
ドレスパッケージＩＣを縦方向に積層して基板に実装す
るようにしたことを特徴とするリードレスパッケージＩ
Ｃの基板実装方法。 ２、複数個のリードレスパッケージＩＣに切込み部を設
けた特許請求の範囲第１項記載のり一ドレスパソケージ
ＩＣの基板実装方法。[Claims] 1. A leadless package I characterized in that a plurality of leadless package ICs each having a desired wiring formed on the side surface are vertically stacked and mounted on a substrate.
C board mounting method. 2. A method for mounting a glueless path cage IC on a board according to claim 1, wherein notches are provided in a plurality of leadless package ICs.
JP1739484A 1984-01-31 1984-01-31 Mounting of leadless package ic for board Pending JPS60160641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1739484A JPS60160641A (en) 1984-01-31 1984-01-31 Mounting of leadless package ic for board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1739484A JPS60160641A (en) 1984-01-31 1984-01-31 Mounting of leadless package ic for board

Publications (1)

Publication Number Publication Date
JPS60160641A true JPS60160641A (en) 1985-08-22

Family

ID=11942781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1739484A Pending JPS60160641A (en) 1984-01-31 1984-01-31 Mounting of leadless package ic for board

Country Status (1)

Country Link
JP (1) JPS60160641A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
US5847448A (en) * 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
USRE36916E (en) * 1995-03-21 2000-10-17 Simple Technology Incorporated Apparatus for stacking semiconductor chips

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847448A (en) * 1990-12-11 1998-12-08 Thomson-Csf Method and device for interconnecting integrated circuits in three dimensions
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
USRE36916E (en) * 1995-03-21 2000-10-17 Simple Technology Incorporated Apparatus for stacking semiconductor chips

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