JPH01235264A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the number of connected points of the title integrated circuit device when it is mounted on a printed substrate and the like by a method wherein, for the semiconductor wafer whereon a large number of integrated circuits to be divided as chips are formed, an interwiring is provided on a plurality of adjacently positioned integrated circuits if necessary, and a plurality of integrated circuit regions are cut out as chips. CONSTITUTION:Each of integrated circuits 11 and 12 is brought into a state wherein it can be cut as a chip through an element formation process, a wiring formation process and a passivation process in accordance with the ordinary integrated circuit manufacturing technique. The integrated circuits 11 and 12 have electrode terminals 2 respectively which are used as bonding pads. There are chip-enabling terminals CE, address terminals A0 and A1..., input and output terminals I/O1, I/O2... and the like in the above-mentioned terminals 2. Said two integrated circuits 11 and 12 are interconnected and interwired between the terminals to be common-connected in the wafer state. After two memory regions have been interwired in the wafer state, the wafers are cut at the positions of A-A, B-B, C-C and D-D and a memory integrated circuit chip 8 is obtained.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to improvements in semiconductor integrated circuit devices.

(Prior Art) Recently, external storage devices for electronic computers and the like that are equipped with a plurality of memory integrated circuits have been developed. In the case of a packaged memory integrated circuit, the method for mounting a memory integrated circuit in such a device is to place it on a printed circuit board and connect the leads of the memory integrated circuit with the wiring on the printed circuit board. The method used is to connect them with solder.

In the case of a bare integrated circuit chip that is not packaged, it is mounted on a printed circuit board, and the electrode terminals of the integrated circuit chip and the wiring on the printed circuit board are connected by wire bonding. For example, a method is used in which a bump electrode is formed on the substrate and then pressure-bonded to the wiring on the printed circuit board.

Higher density packaging is generally possible using integrated circuit chips than using packaged memory integrated circuits. For example, in the case of a small and thin device such as a card-shaped memory integrated circuit device compliant with the ISO standard, it is preferable to mount an integrated circuit chip in order to achieve high density. However, increasing the number of integrated circuit chips to increase memory capacity creates reliability problems. The reliability of this type of memory device depends not only on the reliability of the integrated circuit chips themselves, but also on the reliability of the connections between the integrated circuit chips and the printed circuit board. When connected to a printed circuit board, there are a large number of connection points, which significantly reduces reliability.

(Problems to be Solved by the Invention) As described above, when multiple integrated circuit chips are mounted in a small, thin, and high-density manner, there is a problem that the number of connection points becomes extremely large, resulting in low reliability. Ta.

An object of the present invention is to provide a semiconductor integrated circuit device that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides for a semiconductor wafer on which a large number of integrated circuits are formed, each of which is to be divided into chips, to be divided into a plurality of adjacent integrated circuits, if necessary. With mutual wiring,
Multiple integrated circuit areas cut out as one chip are commonly connected.

(Function) In this way, if multiple integrated circuit areas are interconnected in the wafer state using thin film technology and made into a chip without dividing the area that should originally be divided into chips, it can be mounted on a printed circuit board, etc. The number of connection points can be reduced. For example, when a large capacity memory is obtained by mounting multiple memory integrated circuit chips of a predetermined bit size, the multiple address terminals and multiple input/output terminals of each integrated circuit chip are usually commonly connected during mounting. . If these commonly connected terminals are interconnected in advance in a wafer state and a plurality of chip areas are integrated into one chip, the number of connection parts with a printed circuit board or the like can be greatly reduced. This enables highly reliable, high-density packaging.

Furthermore, even when mutual wiring is not performed in advance, the work efficiency of mounting is lower than the conventional method of cutting out general-purpose integrated circuits such as standard logic into small chips of 2 to 3 IIIN and mounting multiple chips on a wiring board. This will greatly improve performance and reduce implementation costs.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) to 1(d) show the manufacturing process of a memory integrated circuit device according to one embodiment. This embodiment shows a case where two adjacent chip areas are cut out as one chip from a wafer on which a large number of memory integrated circuits are arranged. The figure shows memory integrated circuits 11 and 12 in the two-chip area. (a)
Each integrated circuit shown in 1. , 12 are subjected to element formation, wiring formation steps, and passivation steps according to ordinary integrated circuit manufacturing techniques, and are ready to be cut out as chips. The integrated circuits 11, 12 each have an electrode terminal 2 which is a bonding pad. In the figure, 16 electrode terminals are shown in each case.

These terminals 2 are chip enable terminal CE, address terminal AO+AI, . . . , input/output terminals 1101, 1102, . . . as shown in the figure.

For these two integrated circuits 11.1□, interconnection wiring is performed using thin film technology between terminals to be commonly connected to each other in the wafer state. That is, as shown in (b), a vertical wiring 5 having through-hole terminals 4 is formed in the active region on the passivation film 3. As a result, the electrode terminals 2 arranged around each integrated circuit 11, 12 are drawn out to the internal through-hole terminals 4. Next, as shown in (C), the entire area except for the electrode terminals 2 and through-hole terminals 4 is covered with an insulating film 6. Then, as shown in (d), through-hole terminals 4 to be commonly connected between adjacent integrated circuits 10 and 12 are connected by horizontal wiring 7. Specifically, in this embodiment, the corresponding address terminals AO+ A1 + . l102,
... to be commonly connected.

For example, the chip enable terminals CE, which are left separately as external terminals, are not commonly connected in the above wiring process. After interconnecting the two memory areas in the wafer state in this way, A-A, B-B, C-C, D shown in (d)
- Cut the wafer at position D, and cut the memory integrated circuit chip 8.
get. (e) shows the state in which the cut out memory integrated circuit chip 8 is mounted on, for example, a printed circuit board. Wiring terminals 9 on the printed circuit board and electrode terminals 2 on the chip 8 are connected by bonding wires 10. In the diagram,
Only the terminals 2 necessary for bonding are left, and the electrode terminals 2 unrelated to bonding are left. Suhole terminal 4. Wiring 7 and the like are omitted.

As described above, according to this embodiment, the number of bonding locations can be significantly reduced compared to the case where each of the memory integrated circuits 11.1□ is made into a chip and these are mounted on a printed circuit board. In the case of the above embodiment, a memory with a capacity twice the original capacity of one chip area is obtained, but as mentioned above, terminals to be commonly connected, such as corresponding address terminals, input/output terminals, etc., are made using thin film technology in advance. This is because they are commonly connected before being used and cut into chips.

In the above embodiments, specific techniques for forming the metal thin film serving as wiring include vacuum evaporation, sputtering, plating, and the like. As the insulating film, S i 02, AJ20
3. Sputtering non-materials such as Si3N4 film,
It can be formed by a CVD method or a method of spin-coding an organic material such as polyimide. Photoetching technology, lift-off technology, etc. are used as microfabrication technology for thin films.

As another embodiment, printed wiring may be used to connect the cut out memory integrated circuit chip and the printed circuit board.

In this case, for example, the memory integrated circuit chip 8 shown in FIG. 1(d) is covered with an insulating film 11, leaving the necessary through-hole terminal 4 and electrode terminal 2 areas, as shown in FIG. And exposed through-hole terminal 4 and electrode terminal 2
is connected to the outside using thick film technology. If the electrode terminals shown in FIG. 2 are too small for printed wiring, a printed terminal may be further provided on the insulating film 11. FIG. 3(a) shows the state in which the large printing terminal 12 is arranged, and FIG. 3(b) shows the state in which the large printing terminal 12 is arranged.
2 shows a state in which the lead-out wiring portion of the printing terminal is covered with an insulating film 13. In this way, printed wiring becomes easy.

In the above embodiments, a memory integrated circuit device has been described.

In the case of memory devices, the present invention is particularly effective because many terminals such as address terminals and input/output terminals can be commonly connected when using a plurality of memory integrated circuit chips. can also be applied in the same way. Specifically, for example, an embodiment in which a plurality of blocks of a general-purpose integrated circuit wafer are cut out at once will be described below.

FIGS. 4(a) and 4(b) are enlarged views of a semiconductor wafer on which a plurality of integrated circuits 21 on which input/output terminal electrodes and power supply electrodes are formed are arranged, and a portion of one integrated circuit 21 thereof. As shown in FIG. 4(b), dicing lines 22 and spaces 23 are provided on the semiconductor wafer to serve as a guide for separating and cutting individual integrated circuits. Any one of these may be omitted. In this semiconductor wafer state, a test is performed using the input/output terminal electrodes 24 of each integrated circuit to determine good products and defective products, and then protruding electrodes are formed on the input/output terminal electrodes 24 by soldering or the like. The circuit test may be performed after the protrusion electrodes are formed. Then, by sorting so that only good products are collected, for example, four adjacent integrated circuit blocks are cut out as shown in FIG. For example, if the integrated circuit is a standard logic circuit and is about 3U square, by cutting it out all together in this way, one chip will have a size of about 6H square.

FIG. 6 shows a state in which the assembled integrated circuit thus cut out is mounted on a wiring board 31 by a flip-chip method. A protruding electrode 25 is formed on the input/output terminal electrode formed on the integrated circuit 21, and the protruding electrode 25 is mounted so that this surface faces the surface on which the corresponding electrode of the wiring board 31 is formed.

According to this embodiment, whereas conventionally four times of mounting were required, only one mounting is required, thereby reducing the mounting cost. Also, during mounting, the space required between each chip is eliminated, and the mounting width is improved accordingly.
Furthermore, the larger size of the chip also improves workability.

Further, according to this embodiment, even when a heat dissipation structure is adopted, the seventh
One heatsink 32 for four integrated circuit areas as shown in the figure.
can be glued effectively.

In the conventional method, as shown in FIG. 8(a), heat sinks 321 and 322 must be attached to each small integrated circuit chip 21, which poses a problem in workability. As shown in FIG. 8(b), it is naturally possible to attach a heat sink 32 to a plurality of integrated circuits in common in order to improve workability. However, in this case, there is a possibility that the heat sink may not be reliably bonded due to variations in the height of each integrated circuit when mounted. As a result, the heat dissipation efficiency may not be sufficient. It may be possible to attach the integrated circuit to the heatsink before mounting it on the wiring board, but in that case alignment during mounting becomes difficult. In this embodiment, there is no such difficulty, and a heat dissipation structure having a sufficient heat dissipation effect can be easily realized.

In this example, even if some of the heatsinks are not properly bonded, the substrate constituting each integrated circuit is often silicon, which has good heat conductivity, and can easily spread to the adjacent integrated circuit area. Because the heat is dispersed, a high heat dissipation effect can be obtained.

Note that in order to avoid the effects of thermal stress, it is desirable to select a substrate on which the integrated circuit is mounted that has approximately the same coefficient of thermal expansion as the material constituting the integrated circuit. Specifically, for example, it is preferable that the wiring board is made of the same material as the integrated circuit board.

The invention is capable of further variations. For example, in the embodiment, a semiconductor wafer is described in which integrated circuits all having the same function are formed in an array. The present invention is also effective when cutting out. Further, it is not always necessary to cut along the dicing line, but it is also possible to cut partially across the integrated circuit depending on the size of other chips.

[Effects of the Invention] As described above, according to the present invention, it is possible to solve the problem of an increase in connection points when multiple integrated circuit chips of the same type are combined and mounted, and to perform high-density mounting with high reliability. be able to.

Furthermore, by cutting out multiple integrated circuit blocks at once, workability during mounting is improved, a heat dissipation structure can be easily adopted, and highly reliable high-density mounting is possible.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are diagrams for explaining the terminal connection and mounting method of a memory integrated circuit device according to an embodiment of the present invention,
Figure 2 is a diagram for explaining an embodiment that uses printed wiring, Figures 3 (a) and (b) are diagrams for explaining another embodiment that also uses printed wiring, and Figure 4 (a). )(b) is a diagram showing a semiconductor wafer of another embodiment and one integrated circuit area thereof, FIG. 5 is a diagram showing a chip cut out from the semiconductor wafer, and FIG. 6 is a diagram showing the chip mounted on a wiring board. FIG. 7 is a diagram showing a state in which a heat sink is attached to the mounted integrated circuit, and FIGS. 8(a) and 8(b) are diagrams showing a conventional heat dissipation structure. 11.12...Integrated circuit (memory integrated circuit), 2...
- Electrode terminal, 3... Insulating film, 4... Through hole terminal, 5... Vertical wiring, 6... Insulating film, 7... Horizontal wiring, 8... Memory integrated circuit chip , 9... printed wiring terminal, 10... bonding wire. Applicant's agent Patent attorney Takehiko Suzue Figure 3-1

Claims (9)

[Claims] (1) A semiconductor integrated circuit device characterized in that a plurality of semiconductor integrated circuit blocks are separated and cut as a single chip from a semiconductor wafer on which a large number of semiconductor integrated circuits including wiring and external input/output terminals are formed. . (2) A semiconductor wafer on which a large number of integrated circuits, each of which is to be divided into chips, is arrayed, is interconnected across multiple integrated circuit areas adjacent to each other, and the multiple integrated circuit areas are considered as one unit. A semiconductor integrated circuit device characterized by being cut out. (3) The semiconductor integrated circuit device according to claim 1 or 2, wherein adjacent semiconductor integrated circuits on the semiconductor wafer have bonding terminals and have the same structure. (4) The semiconductor integrated circuit device according to claim 2, wherein the integrated circuit is a memory integrated circuit. (5) The semiconductor integrated circuit device according to claim 2, wherein the mutual wiring connecting adjacent integrated circuits commonly connects corresponding address terminals and input/output terminals. (6) The semiconductor integrated circuit device according to claim 2, wherein the mutual wiring connecting adjacent integrated circuits connects all the bonding terminals other than one bonding terminal that distinguishes the integrated circuits. (7) The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit is a general-purpose integrated circuit. (8) The semiconductor integrated circuit device according to claim 1, wherein protruding electrodes are formed on the input/output electrodes to the outside of the integrated circuit and the power supply electrodes. (9) The semiconductor according to claim 1, wherein the semiconductor integrated circuit is mounted such that the surface on which external input/output electrodes and power supply electrodes are formed faces the surface on which corresponding electrodes are formed on the wiring board. Integrated circuit device.