JPH04118968A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the electric resistance value at signal line connecting sections of different wiring layers so as to increase the signal propagating speed between elements by forming a plurality of contact holes to the signal line connecting sections. CONSTITUTION:This semiconductor integrated circuit device is constituted in such a way that signal inputting-outputting cells are arranged in its peripheral area and functional cells 3, such as an inverter, NAND, NOR, flip flop, etc., are arranged inside, with a wiring area 4 being formed between functional cell 3 arranging rows. Since signal lines are automatically wired, longitudinal and transversal wiring grids exist in the wiring area 4 at regular intervals. The first-layer aluminum wiring 5 and second-layer aluminum wiring 6 are electrically connected with each other through two contact holes 7. Since the two contact holes 7 are provided, the contact areas between the first-layer wiring 5 and second-layer wiring 5 becomes twice as large as that of the conventional signal line wiring contact hole section.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device manufactured by applying a master slice method or a standard cell method, and particularly relates to a semiconductor integrated circuit device manufactured by applying a master slice method or a standard cell method. The present invention relates to a connection method between signal wirings.

[Prior Art] In a semiconductor integrated circuit device manufactured by applying the conventional master slice method or standard cell method, the first layer aluminum wiring 5 has one contact hole, as shown in FIGS. 4 and 5. It was connected to the second layer aluminum wiring 6 through 7.

Problem to be Solved by the Invention 1 However, in the above-mentioned prior art, the first layer aluminum wiring 5 and the
Since the contact area with the layered aluminum wiring 6 is small, the electrical resistance at the contact hole portion is large, and in a signal wiring that passes through many contact holes in series, there is a problem that the signal propagation delay time becomes large. Furthermore, there are many semiconductor chips that are defective due to defective contact holes in some of the semiconductor chips, which causes a decrease in yield.

The present invention is intended to solve these problems, and its purpose is to provide a semiconductor integrated circuit that further reduces the electrical resistance value in the signal wiring contact hole portion, improves the propagation delay speed, and improves the yield. It is located where the equipment is provided.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the semiconductor integrated circuit device of the present invention has a semiconductor integrated circuit device manufactured by applying a master slice method or a standard cell method. A plurality of contact holes are provided for establishing electrical continuity between one signal wiring wired on the wiring grid and one signal wiring wired on the wiring grid of a wiring layer different from the wiring layer. Features.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing a semiconductor integrated circuit according to the present invention. Cells 2 are arranged around the periphery for signal input/output, and functional cells 3 such as inverters, NANDs, N○Rs, and flip-flops are arranged inside, and the west [! A line area 4 is provided. Since signal wiring is performed by automatic wiring, wiring grids exist in the wiring area 4 at regular intervals in the vertical and horizontal directions.

FIG. 2 is a drawing showing a signal wiring contact hole portion of the present invention. The first layer aluminum wiring 5 and the second layer aluminum wiring 6 are electrically connected through two contact holes 7.

FIG. 3 shows a cross section taken along line AA' in FIG. In order to have two contact holes, first layer aluminum wiring 5 and 2 are connected.
The contact area with the layered aluminum wiring 6 is twice the contact area of the conventional signal wiring contact hole shown in FIGS. 4 and 5.

[Effects of the Invention] According to the present invention, with a simple structure in which a plurality of contact holes are provided in the signal wiring connection portions of different wiring layers, the electrical resistance value of the connection portions can be reduced. This has the effect of improving the signal propagation speed between the contact holes and the reduction in yield due to poor conduction in the contact hole portion.

Furthermore, the effects of the present invention are more pronounced as the signal wiring width becomes smaller, and it is believed that the present invention is extremely useful for master slice type and standard cell type semiconductor integrated circuit devices, which are becoming increasingly finer and multilayered.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit device according to the present invention. FIG. 2 is a diagram showing a contact hole portion of the semiconductor integrated circuit device of the present invention. FIG. 3 is a sectional view taken along the line A-A' in FIG. FIG. 4 is a diagram showing a contact hole portion of a conventional semiconductor integrated circuit device. FIG. 5 is a sectional view taken along line BB' in FIG. Semiconductor chip input/output cell functional cell wiring range 1st layer aluminum wiring, 2nd layer aluminum wiring, contact hole, semiconductor substrate, interlayer insulating film Applicant: Yoshiko Epson Corporation Patent attorney Kizobe Suzuki ( 1 person) Figure 2 Figure 3

Claims (1)

[Claims] In a semiconductor integrated circuit device manufactured by applying the master slice method or the standard cell method, one signal wire is wired on a wiring grid of one wiring layer, and one signal wire is wired on a wiring grid of a wiring layer different from the aforementioned wiring layer. A semiconductor integrated circuit device characterized in that a plurality of contact holes are provided for establishing electrical continuity with one signal wiring.