JPS59135744A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the decrease in working speed of the titled device by a method wherein, in the case of the LSI or VLSI of master slice system, the wiring between fundamental cells is formed using a low resistance wiring material. CONSTITUTION:In the LSI or VLSI of master slice where a fundamental cell is formed using a CMOS, the fundamental cell 3 to be formed on a semiconductor substrate has an N type region 7, a P type region 8 and gate electrodes 9, 10 and 11 formed in Y-direction with a polycrystalline silicon. Wirings 14, 15, 18, 19 and 20 are formed in X-direction as the second layer on the gate electrodes 9, 10 and 11 using the low resistance material such as aluminum and the like through the intermediary of an interlayer insulating film. The wiring 14 is connected to the source voltage, and the wiring 15 is grounded, and the wirings 18, 19 and 20 are provided for the purpose of transmission of the signal between fundamental cells. A wiring 21 is formed in Y-direction on the wirings 14, 15, 18, 19 and 20 as the third layer using a low resistance material through the intermediary of an interlayer insulating film, and it is connected to the gate electrode 9 and the wirings 19 and 20 using a through hole.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale integrated circuit [LSI (LargeSca
very large scale integrated circuit (VLSI)], very large scale integrated circuit (VLSI)
This invention relates to the improvement of semiconductor integrated circuit devices such as tegrat-ion).

There are various types of semiconductor integrated circuit devices using the so-called master slice method, in which a plurality of semiconductor elements are divided into one basic cell, integrated on a semiconductor chip, and a logic circuit is configured by this basic cell or a combination of basic cells. There is a strong demand for its adoption in order to supply semiconductor integrated circuits that are compatible with the logical functions of .

In such a master slice type semiconductor integrated circuit device,
The layout form of the basic cells that make up the system is fixed, and the wiring form between the basic cells is automatically determined or changed by a computer. This is so-called automatic wiring, which configures functions that quickly respond to the demands of customers. be. This provides various integrated circuit devices that are compatible with the circuit functions of semiconductor integrated circuit devices.

In such a master slice type semiconductor integrated circuit device, when configuring some kind of logic circuit, the wiring form is extremely often limited by the area of the wiring region provided between basic cells.

As a result, some basic cells are left unwired, and manual wiring has to be performed to remove these unwired basic cells.

For this purpose, it is conceivable to utilize a predetermined basic cell or a portion of a semiconductor element (a part of the basic cell) provided for configuring the predetermined basic cell. A part of this semiconductor element is, for example, an insulated gate field effect transistor (hereinafter referred to as MOSFET (Metal Oxide Semi)).
conductor Field Eff-ect T
transistor)]. This gate electrode is usually provided with portions that serve as terminals at both ends, and these portions are arranged at the periphery of the basic cell. Therefore, effectively utilizing such a gate electrode as a wiring alleviates restrictions on the wiring form between basic cells, and is extremely advantageous in terms of the configuration of a logic circuit.

However, when the gate electrode is inserted into the wiring between basic cells, high resistance is added between the wirings. This is because the gate electrode material has a higher resistance value than the wiring material between basic cells. This has the disadvantage that the operating speed of the semiconductor integrated circuit device is significantly reduced, which is unfavorable in terms of the performance of the semiconductor integrated circuit device.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, to provide a semiconductor integrated circuit device that is not limited by the wiring form for configuring logic circuits, etc., and that does not reduce performance such as operating speed. It is about providing.

Hereinafter, the present invention will be explained in detail along with an example.

In addition, in all the figures, parts having similar functions are given the same symbols, and repeated explanations thereof will be omitted.

In this embodiment, a complementary insulated gate field effect transistor (CMOS (Complementary Mat
An explanation will be given using a basic cell which is made of Al Oxide Semiconductor) and which can constitute a three-input type NAND gate circuit.

FIG. 1 is a schematic diagram for explaining a semiconductor integrated circuit device of the present invention.

In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device, which is constituted by a semiconductor substrate 2 made of silicon single crystal or the like. A basic cell 3 is provided in the center of the semiconductor substrate 2, and is used to configure a logic circuit by one basic cell or a combination of a plurality of basic cells.

The basic cell is partially or entirely composed of semiconductor elements made up of a plurality of CMOS. Reference numeral 4 denotes an external terminal provided on the periphery of the semiconductor substrate 2, which is used to send and receive signals from the outside of the semiconductor integrated circuit device 1 to the integrated circuit consisting of a plurality of internal logic circuits, or in the opposite direction. It is. Reference numeral 5 denotes an input/output buffer circuit provided around the external terminal and between the external terminal 4 and the integrated circuit, and for controlling the signal level from the external terminal 4 to the integrated circuit or in the opposite direction. belongs to.

The spaces between the columns L of elementary cells 3 are not shown or are provided with interconnections for providing logic functions. The mutual wiring is composed of a first layer of polycrystalline silicon layer for providing a CMOS gate electrode, a second layer of wiring, and a third layer of wiring. These three wiring layers are electrically isolated from each other by an interlayer insulating film (not shown). The second wiring layer and the third wiring layer
As the material for the second wiring layer, a low resistance material such as aluminum, which has a lower resistivity than polycrystalline silicon used as the gate electrode, is used. As will be made clear from the explanation of FIG. 2, which will be described later, the electrode of the first layer of polycrystalline silicon constituting the gate electrode of the basic cell is oriented in a predetermined direction (
The second wiring layer is arranged at a predetermined pitch in the direction (Y direction), the second layer is arranged at a predetermined pitch in the direction crossing this (X direction), and the third layer The wiring layer of
They are arranged at a predetermined pitch in the direction (Y direction) intersecting the second wiring layer.

That is, the multilayer wiring layers for mutual wiring are arranged so that two adjacent layers are orthogonal to each other. As a master slicing method for providing various integrated circuit devices with different logical functions, the positions of contact holes in the wiring layer relative to the semiconductor element area and the positions of through holes provided in the interlayer insulating film between the wiring layers are appropriately adjusted. choose,
Thereby, the wiring form of mutual wiring can be changed. This master slicing method enables automatic wiring by computer by displaying the positions of the first, second, and third wiring layers as well as the positions of contact holes and through holes in virtual coordinates. It is.

FIG. 2 is a plan view showing wiring in a basic cell portion and its peripheral portion in the semiconductor integrated circuit device of the present invention shown in FIG. In accordance with the present invention, an example is shown in which a part of the system wiring providing a predetermined logical function is wired using a part of a predetermined basic cell. This structure will be explained below. Note that in order to simplify the explanation, an insulating film to be provided between each layer is not shown.

In FIG. 2, 3 is a predetermined basic cell provided on the semiconductor substrate 1, and has a function as a part of a logic circuit.
In addition, this is intended to alleviate restrictions imposed by wiring configurations. A predetermined basic cell 3 is constituted by an N type region 7 having an N type impurity and a P type region 8 having a P type impurity. 910 and 11 are N-type region 7 and P-type region 8
This is the first layer gate electrode provided above, and portions serving as terminals for connection to wiring are provided at both ends of the gate electrode. The gate electrodes 9, 10, 11 are formed by applying a voltage to the N-type region 7 under the gate electrode.
and for forming a channel region near the surface of the P-type region 8.

This gate electrode is made of a material that can withstand the heat treatment for forming the source and drain regions, and is made of a stable C
The material is selected to be able to provide the threshold voltage (V_t_h) of the MOSFET. Polycrystalline silicon is chosen as this most preferred material. In this case, the resistivity of polycrystalline silicon is high, so the gate electrode has a high resistance. Reference numeral 12 denotes a semiconductor region having a P^+ type impurity, which is provided in the N type region 7 on both sides of the gate electrodes 9, 10, and 11, and has conductivity. Reference numeral 13 denotes a semiconductor region having an N^+ type impurity, which is provided in the P type region 8 on both sides of the gate electrodes 9, 10, and 11, and has conductivity.

Reference numeral 14 denotes a second-layer horizontal (hereinafter referred to as X) wiring, which is connected to the V_D_D voltage power source to apply the V_D_D voltage. The X wiring 14 is connected to the semiconductor region 12 via the contact hole C. 1
Reference numeral 5 indicates an X wiring, which is at ground potential. X wiring 15
is connected to the semiconductor region 13 via a contact hole C. The wiring 16 has one end connected to the semiconductor region 12 on the drain (D) side of the MOSFETQ_1 formed by the gate electrode 10 through the contact hole C, and connects to the semiconductor region 12 on the drain (D) side of the MOSFETQ_1 formed by the gate electrode 11.
The MOSFE is connected to the semiconductor region 12 on the drain (D) side of 2 through the contact hole C, and the other end is bent at a right angle, and is formed by the gate electrode 11.
It is connected to the semiconductor region 13 on the drain (D) side of TQ_3 through a contact hole C. Reference numeral 18 denotes an X wiring whose one end is connected to the wiring 16 by a through hole T, and whose other end is connected to another basic cell for outputting the signal of a predetermined basic cell 6 to the other basic cell. be.

Reference numeral 19 denotes an X wiring provided in a wiring area between basic cells, one end of which is connected to another basic cell A, and is used to transmit an output signal from the basic cell A. Reference numeral 20 denotes an X wiring provided in another wiring area between the basic cells, one end of which is connected to another basic cell B, and is used to transmit the output signal from the basic cell A to the basic cell B. be.

21 is a vertical (hereinafter referred to as Y) wiring, which is provided above the gate electrode 9 of a predetermined basic cell 3 with an insulating film interposed therebetween;
One end is connected to the other end of the X wiring 20 by the through hole T, and the other end is connected to the other end of the X wiring 19. Further, the Y wiring 21 and the gate electrode 9 are connected through a contact hole C_1. As a result, the other basic cell A and the other basic cell B are electrically connected,
Moreover, it is connected to the wiring between basic cells A and B, and becomes part of the logic circuit. All the X wirings are formed at the same time in one process, and all the Y wirings are formed at the same time in another process. Said X
For the wiring and the Y wiring, a high melting point metal wiring material such as aluminum (Al), molybdenum (Mo), or titanium (Ti), or a low resistance wiring material such as silicide, which is a compound of silicon (Si), may be used.

Thereby, the predetermined basic cell 3 can be configured as a part of a logic circuit, and a part thereof can be used as wiring.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof. For example, although some of the semiconductor elements of the basic cell were used in the above embodiments, it is of course possible to use all the semiconductor elements.

As described above, according to the present invention, in a semiconductor integrated circuit device, at least a portion of predetermined basic cells used for configuring a logic circuit can be used to provide wiring between basic cells. As a result, any logic circuit can be easily configured without any restrictions on the wiring form between basic cells.

Furthermore, it is possible to realize low-resistance wiring between all basic cells. Therefore, the operating speed can be increased and the performance of the semiconductor integrated circuit device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram for explaining a semiconductor integrated circuit device of the present invention, and FIG. 2 is a plan view of a main part of the semiconductor integrated circuit device for explaining an embodiment of the present invention. In the figure, 1... semiconductor integrated circuit device, 2... semiconductor substrate, 3... basic cell, 4... external terminal, 5... input/output buffer circuit, 6... predetermined basic cell ,7...
N-type region, 8... P-type region, 9, 10, 11... gate electrode, 12, 13... semiconductor region, 14-21.
...Wiring, C, C_1...Contact hole, T...
-Through hole.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device such as a large-scale integrated circuit or a very large-scale integrated circuit in which a plurality of basic cells are arranged, all wirings to connect the basic cells are made of a low-resistance wiring material. A semiconductor integrated circuit device characterized by: 2. A semiconductor integrated circuit device such as a large-scale integrated circuit having a plurality of basic cells arranged, such as a very large-scale integrated circuit, characterized in that all wirings to connect the basic cells are made of a low-resistance wiring material. A semiconductor integrated circuit device, characterized in that at least one of the wirings is provided in at least a part of a predetermined basic cell between basic cells, and the wiring and the predetermined basic cell are connected. Integrated circuit device.