JPH0519303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a wiring shape that prevents short-circuiting and disconnection of upper-layer wiring by devising a wiring pattern in a semiconductor integrated circuit device that is a semiconductor device having a multilayer wiring structure.

(Prior Art) As the degree of integration increases in semiconductor integrated circuit devices, it has become inevitable to adopt a multilayer wiring structure. Although the multilayer wiring structure has the major advantages of facilitating design by increasing the topological freedom of wiring and reducing chip area by reducing the wiring area, As a result, accidents such as short circuits and disconnections in upper layer wiring are more likely to occur. In particular, when lower-layer wiring runs in parallel with narrow wiring intervals, the interlayer insulator may not be filled evenly in the wiring interval, or the interlayer insulator at the stepped portion of the lower-layer wiring in the wiring interval may face each other in a flaw-like manner. As a result, the step coverage of the upper layer metal at the step becomes extremely poor (Shadowing effect), leading to wiring problems such as breakage of the upper layer wiring and shortened wiring life. It is aroused.

(Object of the Invention) An object of the present invention is to provide an effective semiconductor device, particularly a semiconductor integrated circuit device, which eliminates the above-mentioned drawbacks.

(Structure of the Invention) The present invention provides for a plurality of lower layer wirings arranged in parallel with such narrow wiring intervals, at a location where the lower layer wiring intersects with an upper layer wiring arranged perpendicularly through an interlayer insulator. By increasing the wiring spacing on two opposing sides of the wiring spacing section of the lower layer wiring, the degree of coverage (Step
The goal is to improve coverage. A feature of the present invention is that first and second lower layer wirings are provided in parallel with each other at a predetermined wiring interval on an insulating film formed on the main surface of a semiconductor substrate, and the second lower layer wiring is
The insulating film is formed continuously with a flat upper surface down to the lower wiring, and an interlayer insulating layer is formed by continuously covering the first and second lower wiring and the insulating film therebetween. In a semiconductor device in which an upper layer wiring is provided orthogonally to the first and second wirings in such a manner that all portions of the upper layer wiring are located on the interlayer insulating layer, The two opposing sides of the first and second lower-layer wirings are each further away from the other wiring than other parts, thereby making the wiring spacing at the crossing point wider than other parts, and In the semiconductor device, the other two sides of each of the first and second lower-layer wirings are in a straight line including the intersection. As described above, in the present invention, the wiring spacing for improving the coverage is increased not depending only on one lower layer wiring, but on each of two opposing lower layer wirings. That is, in order to form a predetermined wiring interval that is enlarged at the intersection, opposing recesses are formed in each lower layer wiring. Therefore, the depth of the opposing recesses of one lower layer wiring can be kept to the minimum necessary, and this eliminates the problem of increased electrical resistance due to the narrower width of the lower layer wiring at the intersection point, and the pattern of the lower layer wiring. It is possible to prevent the occurrence of cutting problems.

(Explanation of Examples) Next, the present invention will be explained using the drawings.

FIG. 1 shows the prior art, in which a first layer wiring 3 is disposed on a silicon oxide film 2 formed on the surface of a silicon substrate 1, and after it is covered with an insulator 4,
3 is a cross-sectional view showing a state in which second layer wiring 5 is arranged orthogonally to first layer wiring 3. FIG. The second layer wiring 5, which is disposed perpendicularly to the first layer wiring 3 with an interlayer insulator 4 interposed on the first layer wiring 3, which is arranged in parallel with a narrow wiring interval, is stepped at the narrow wiring interval. The diagram shows how it is cut. FIG. 2 is a plan view of the state shown in FIG. 1. The second layer wiring 7, which is disposed orthogonally to the first layer wiring 3 running in parallel with narrow wiring intervals, is shown to be disconnected at 8 and 9 of the wiring interval.

FIG. 3 is a plan view of the multilayer wiring structure according to the embodiment of the present invention at the time when the etching of the second layer wiring is completed. In other words, at the intersection of the first-layer wiring 10 running in parallel with the second-layer wiring 13, the two opposing sides of the first-layer wiring spacing section are set back to widen the wiring spacing. . Since the wiring spacing is widened in the recesses 11 and 12 of the first layer wiring, the degree of coverage of the second layer wiring in the wiring spacing is greatly improved. Figure 4 is A- in Figure 3.
FIG. 3 is a sectional view of part A′. A second layer wiring 13 runs on the first layer wiring 10 running in parallel with an interlayer insulator 15 interposed therebetween. Since the distance between the first layer wiring at the intersection of the first and second layer wiring is widened, the shadowing effect when depositing interlayer insulators and upper layer wiring metal is eliminated, and the step of the first layer wiring is increased. A second layer wiring having good coverage in the area is obtained.

If the wiring pattern structure of the present invention is adopted,
In semiconductor integrated circuits, where the degree of integration is increasing,
The stability of wiring formation is increased, and the yield of non-defective products can be improved.

[Brief explanation of drawings]

1 and 2 are a sectional view and a plan view showing the prior art, and FIGS. 3 and 4 are a plan view and a sectional view showing an embodiment of the present invention. In addition, in the figure, 1... silicon semiconductor substrate,
2...Insulating film such as silicon dioxide oxide film, 3,1
0...First layer wiring layer which is lower layer wiring, 5,1
3...Second wiring layer which is upper layer wiring, 4,1
5... Interlayer insulator such as CVD silicon dioxide.

Claims (1)

[Claims] 1. First and second lower layer wirings are provided in parallel with each other at a predetermined wiring interval on an insulating film formed on the main surface of a semiconductor substrate, and a line extends from below the first lower layer wiring to below the second lower layer wiring. The insulating film is formed continuously with a flat upper surface, and an interlayer insulating layer is provided to continuously cover the first and second lower wirings and the insulating film between them, and the upper wirings are formed continuously. In a semiconductor device that is provided perpendicularly to the first and second wirings in such a manner that all portions thereof are located on the interlayer insulating layer, the first and second wirings intersect with the upper layer wirings. The two opposing sides of the lower layer wiring are each further away from the other wiring than the other parts, thereby making the wiring spacing at the intersection larger than the other parts, and 2. A semiconductor device characterized in that the other two sides of each of the two lower layer wirings are in a straight line including the intersection point.