JPH04318957A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce resistance without increasing an occupying area of a polysilicon wiring inside a semiconductor chip by providing a first polysilicon film and a second polysilicon film running in parallel thereunder on a multi-level intersection part of the wiring for being connected by through holes. CONSTITUTION:A first wiring 8 consisting of an aluminium film is provided in prescribed sequences. This first wiring 8 and a first polysilicon film 5 at a multi-level intersecting lower layer are connected by through holes 6a, 6b so as to provide the second wirings 7a, 7b multi-level intersecting the first wiring 8. Then, a second polisilicon film 2 at a lower layer is connected to the first silicon film 5 through the through holes 4a, 4b. Thereby, electric resistance between the first wiring 8 and the second wirings 7a, 7b can be reduced because the second polysilicon layer 2 and the through holes 4a, 4b are added as parallel resistance portions as compared with a former one.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, it relates to wiring of semiconductor integrated circuits.

0002

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit such as an EPROM having aluminum wiring and polysilicon wiring, when it is necessary to cross aluminum wirings in the same layer that transmit different signals, one wiring is connected to the other as shown in FIG. (Second wirings 7a, 7b) can be intersected three-dimensionally by using the first polysilicon film at the intersection.

FIG. 2(a) is a plan view of a conventional semiconductor chip, and FIG. 2(b) is a sectional view taken along the line X--X in FIG. 2(a). A second wiring 7a made of an aluminum film is connected to the first polysilicon film 5 through a through hole 6a.
First polysilicon film 5 is connected to aluminum wiring (second wiring 7b) through through hole 6b. It can be seen that at this time, the aluminum wirings (first wirings) transmitting different signals cross three-dimensionally and do not contact the second wirings 7a, 7b and the first polysilicon film 5.

0004

[Problems to be Solved by the Invention] In the conventional three-dimensional intersection structure, when it is necessary to reduce the resistance of the first polysilicon film, it is necessary to reduce the resistance of the first polysilicon film in the parallel direction along the aluminum wiring (8) as shown in FIG. The width of the polysilicon film No. 1 was widened. Although this can reduce electrical resistance, the area occupied by the mask pattern of the semiconductor integrated circuit increases. If there are many places in a semiconductor integrated circuit where the width of the first polysilicon film is widened, the area of the semiconductor chip containing the semiconductor integrated circuit increases and the degree of integration decreases, resulting in the number of chips that can be manufactured within one wafer. There is a problem in that the chip production cost decreases and the chip production cost increases.

[0005]

Means for Solving the Problems The present invention provides a method for connecting a first wiring made of a conductive film in a predetermined layer order to a lower first polysilicon layer that three-dimensionally intersects the first wiring through a through hole. In a semiconductor integrated circuit having a second wiring which is made of a conductive film of a predetermined layer and intersects the first wiring, a second polysilicon film underlying the first polysilicon film is connected through a through hole. It is connected to the first polysilicon film.

[0006]

Embodiment FIG. 1(a) is a plan view of a semiconductor chip showing an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line X--X in FIG. 1(a).

In this embodiment, a first wiring 8 made of an aluminum film in a predetermined layer order, a lower first polysilicon film 5 that three-dimensionally intersects with the first wiring 8, and through holes 6a, 6 are formed.
In a semiconductor integrated circuit having second wirings 7a and 7b which are connected to each other by a polysilicon film 5 and are made of an aluminum film and intersect with the first wiring 8 in a three-dimensional manner, the second wirings 7a and 7b are connected at Polysilicon film 2 forms through hole 4a
, 4b to the first polysilicon film 5.

That is, the second polysilicon film 2 is placed under the first polysilicon film 5 of the conventional three-dimensional intersection structure, and the first polysilicon film 5 and the second polysilicon film 2 are connected by through holes. Connect with 4a and 4b. This allows the first
The electric resistance between the wiring 7a and the second wiring 7b can be made smaller than that in the conventional wiring because the second polysilicon film 2 and the through holes 4a, 4b are added as parallel resistance components.

As for the through-holes 4a and 4b, if there is no problem in the semiconductor manufacturing process, only one of them is used to form a contact surface between the first polysilicon film and the second polysilicon film of the through-hole. By widening it, the resistance can be made even lower.

In the case of a semiconductor integrated circuit incorporating an EPROM, the second polysilicon film can be a polysilicon film in the same layer as the floating gate. Therefore, it is advantageous because no special polysilicon film formation process is required to lower the resistance of the three-dimensional intersection.

[0011]

[Effects of the Invention] As explained above, the present invention provides a first polysilicon film at a three-dimensional intersection of interconnections, and a second polysilicon film running parallel to the first polysilicon film underneath, and connects them with through holes. Therefore, it is possible to reduce the resistance without increasing the area occupied by the polysilicon wiring within the semiconductor chip.

[Brief explanation of the drawing]

FIG. 1 is a plan view (FIG. 1(a)) and a cross-sectional view (FIG. 1(b)) of a semiconductor chip showing one embodiment of the present invention.

[Fig. 2] A plan view of a semiconductor chip showing a conventional example (Fig. 2(a)
)) and a cross-sectional view (FIG. 2(b)).

FIG. 3 is a plan view of a semiconductor chip used to explain the drawbacks of the conventional example.

[Explanation of symbols]

1 Semiconductor substrate 2 Second polysilicon film 3, 3-1, 3-2 Insulating film 4a, 4b Through hole 5 Second polysilicon film 6a, 6a1, 6a2, 6b, 6b1, 6b2
Through holes 7a, 7b Second wiring 8 First wiring

Claims (1)

[Claims] 1. A first wiring made of a conductive film in a predetermined layer and connected to a lower first polysilicon layer that three-dimensionally intersects with the first wiring through a through hole and made of a conductive film in the predetermined layer. In a semiconductor integrated circuit having a second wiring that intersects with a first wiring, a second polysilicon film underlying the first polysilicon film connects to the first polysilicon film through a through hole. A semiconductor integrated circuit characterized by being connected.