JPH01274451A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a constitution wherein the area of the connecting part of wiring layers is not changed even if the aligning parts of mask patterns are deviated, by forming a cross patterns for contact holes by which lower wiring layers that are provided on an insulating film formed on a semiconductor substrate is connected to upper wiring layers that are provided through an interlayer insulating films. CONSTITUTION:This integrated circuit is composed of the following parts: lower wiring layers 1 which are provided on an insulating film formed on a semiconductor substrate; an interlayer insulating film 2 which is provided on the surface including the lower wiring layers 1; cross shaped contact holes 3a which are provided on the interlayer insulating film 2 on the lower wiring layers 1; and upper wiring layers 4 which are provided on the interlayer insulating film 2 and electrically connected to the lower wiring layers at the contact holes 3a. Both ends of each contact hole 3a are extending to the outer side than the overlapped part of the lower wiring layer 1 and the upper wiring layer 4. An area where the lower wiring layer 1 and the upper wiring layer 4 are connected is the same as the area of a conventional contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit.

[Conventional technology]

In recent years, in order to reduce the manufacturing cost and manufacturing time of LSI (Large-Scale PA Integrated Circuits), elements such as transistors and resistors are formed in advance on a semiconductor substrate, and these elements are connected with wiring layers. Semiconductor integrated circuits employing a master slice method for realizing various LSIs are known.

In this method, it is possible to manufacture a wide variety of LSIs in a short period of time by simply replacing the mask for forming the wiring layer, without having to recreate the element-forming (diffusion system) mask. In particular, in the master slicing method for gate arrays, the mask for the wiring layer is currently automatically formed using an automatic wiring program.

In the master slicing method for gate arrays, a dedicated area for wiring (hereinafter referred to as automatic wiring area) is formed in advance to make automatic wiring easier to assemble, and wiring is placed on this area at predetermined intervals. designed to be placed.

FIG. 3 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit.

As shown in the figure, a lower layer wiring 1 provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film 2 provided on the surface including the lower layer wiring 1, and an interlayer insulating film 2 on the lower layer wiring 1. The square or rectangular contact hole 3b provided and the interlayer insulating film 2
It is configured to include an upper layer wiring 4 provided above and electrically connected to the lower layer wiring 1 of the contact hole 3b.

In addition, A is the interval between the lower layer wirings 1, B is the width of the lower layer wiring 1, C is the margin width taking into account misalignment of the contact pattern between the lower layer wiring 1 and the upper layer wiring 4, and D is the width of the upper layer wiring 4. Each is shown below. The above A to D are determined by the capability of the manufacturing process, and as a result, the mutual spacing between the center lines of the lower layer wiring 1 (hereinafter referred to as wiring pitch) E is the minimum spacing determined by the manufacturing process in the gate array master slice method. Placed.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, in order to increase the margin width C of the contact, the width B of the upper layer wiring and the lower layer wiring,
It is necessary to increase each of D, and as a result, the wiring pitch E also increases, which increases the automatic wiring area and increases the chip area, resulting in a problem that the yield of semiconductor chips decreases.

Furthermore, if the margin for misalignment of the mask pattern is made smaller, misalignment will occur and the area of the contact that connects the lower layer wiring 1 and the upper layer wiring 4 will become smaller and the contact resistance will increase, making it difficult to make a normal connection. The disadvantage is that you will not be able to obtain it.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a lower wiring provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film provided on a surface including the lower wiring, and an interlayer insulating film on the lower wiring. The semiconductor device has a cross-shaped contact hole provided therein, and an upper layer wiring provided on the interlayer insulating film and connected to the lower layer wiring of the contact hole.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip for explaining one embodiment of the present invention.

As shown in the figure, a lower layer wiring 1 provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film 2 provided on the surface including the lower layer wiring 1, and an interlayer insulating film 2 on the lower layer wiring 1. The structure includes a cross-shaped contact hole 3a provided, and an upper layer wiring 4 provided on the interlayer insulating film 2 and electrically connected to the lower layer wiring 1 of the contact hole 3a, where A is the mutual spacing of the lower layer wiring 1, B shows the width of the lower layer wiring 1, C shows the margin width in consideration of misalignment of contact patterns between the lower layer wiring 1 and the upper layer wiring 4, D shows the width of the upper layer wiring 4, and E shows the wiring pitch.

Here, the four ends of the contact hole 3a protrude outward beyond the portion where the lower layer wiring 1 and the upper layer wiring 4 overlap, and the area where the lower layer wiring 1 and the upper layer wiring are connected is smaller than that of a conventional contact. It was established on the same area as the hall. If the contact hole 3a is misaligned,
As shown in FIG. 2, even when the contact hole 3a is offset from the center of the overlapping portion of the lower layer wiring 1.4, the connection area between the lower layer wiring 1 and the upper layer wiring 4 remains constant.

Further, since the margin width C can be set larger than before, it is possible to prevent the contact area from being reduced due to contact misalignment without changing the mutual spacing A and the wiring pitch E, thereby improving the reliability of the contacts.

〔Effect of the invention〕

As explained above, the present invention provides a cross-shaped contact hole for connecting a lower layer wiring provided on an insulating film provided on a semiconductor substrate and an upper layer wiring provided via an interlayer insulating film. As a result, even if misalignment of the mask pattern occurs, the area of the connection between wiring layers can be prevented from changing, and as a result, the wiring pitch can be reduced, and the automatic wiring area can also be reduced. This has the effect of reducing the size of the semiconductor chip and increasing the yield of the semiconductor chip.

[Brief explanation of the drawing]

1 and 2 are plan views of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 3 is a plan view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Lower layer wiring, 2... Interlayer insulating film, 3a, 3b.
... Contact hole, 4... Upper layer wiring, A... Interval between lower layer wiring, B... Width of lower layer wiring, C... Alignment margin width of contact pattern, D... Upper layer wiring Width, E... Wiring pitch.

Claims (1)

[Claims] A lower wiring provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film provided on a surface including the lower wiring, and a cross-shaped contact hole provided in the interlayer insulating film on the lower wiring; A semiconductor integrated circuit comprising an upper layer wiring provided on the interlayer insulating film and connected to the lower layer wiring of the contact hole.