JPH0586866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a master slice type semiconductor integrated circuit.

[Conventional technology]

Conventionally, in the manufacture of master slice type semiconductor integrated circuits, first a semiconductor substrate (usually referred to as a master slice) having a structure in which cells each consisting of a plurality of elements such as transistors and resistors are arranged in an array within a chip is manufactured. It is prepared in a completed form up to a process that can be processed all at once (usually referred to as a master process). Next, in the wiring process, metal wiring such as aluminum is used to connect multiple elements of one or more cells to each other to form a circuit block, and also to connect the circuit blocks to achieve the desired result. Large-scale integrated circuits with functions (hereinafter referred to as
The method used was to derive a group (denoted as LSI).

By adopting this method, the labor and time required to design and manufacture each LSI type are reduced only to the part related to the wiring process that uses a layout pattern unique to each type. This is significantly reduced compared to designing a dedicated board for this purpose. In the master slice described above, in order to further shorten the development period of LSI products, it is necessary to save labor in designing wiring process patterns. For this purpose, in recent years, it has become common to automate the arrangement of circuit blocks and the wiring design between circuit blocks, and also to simplify and even automate the wiring design within circuit blocks.

A chip layout structure that enables simplification and automation of the master slice wiring process design will be described with reference to the drawings.

FIG. 3 is a layout diagram of an example of a conventional master slice type semiconductor chip.

The chip 1 is composed of a peripheral area 2 where pads, input/output circuit cells, etc. are placed, and an internal cell array area 3. The internal cell array region 3 includes an internal cell column 5 in which internal cells 4 each consisting of a plurality of transistors and resistors are arranged in the x direction. An inter-internal cell wiring region 6 is provided between the internal cell rows 5 . Normally, the x-direction (horizontal direction) pitch and y-direction (vertical direction) pitch of the internal cell arrangement are uniformly determined in consideration of automatic design and the like.

Regarding the wiring process pattern unique to each LSI type used on the master board layout structure described above, the case where two wiring layers are used will be explained using FIG. 4.

FIG. 4 is a layout diagram of an example of an internal cell array unit repeating unit centered on one internal cell of a conventional bipolar ECL circuit master slice.

In these internal cells, each transistor 1
Not only the arrangement of 0 and resistor 11, but also the contacts 12 of each transistor and resistor, and the single-layer wiring pattern 13 for electrodes covering the contacts, are determined at the master slice design stage, regardless of the difference in LSI type.
Uniformly designed. A circuit block (hereinafter simply referred to as a block) is constructed by using a plurality of internal cells and interconnecting the electrodes of the elements in each cell. Connections between elements are mainly made using one-layer wiring arranged on the inter-element wiring area 14 in the internal cell, but if one-layer wiring alone is insufficient, blocks can be connected using multiple cells adjacent in the y direction. In this case, two-layer wiring is also used. Within each block, block terminal positions are appropriately defined in preparation for later interconnection between blocks. Next, multiple types and multiple blocks are arranged on the internal cell array, and the block terminals are interconnected to form individual LSIs.
The variety is completed.

For connections between blocks, an internal inter-cell wiring area 6 is used.
The first-layer wiring runs in the x direction inside the cell row, and the y
This is done using two-layer wiring that runs in the same direction. Normally, in preparation for the automatic design of interconnects between blocks, paths (hereinafter referred to as tracks) 15 that allow placement of x-direction interconnects between first-layer blocks and y-direction interconnect tracks 16 between second-layer blocks are set. Furthermore, in preparation for the simplification and automation of the block design, an x-direction wiring track 17 for one-layer block configuration (hereinafter referred to as "intra-block") and a y-direction wiring track 18 for one-layer block configuration are provided.
is set. Regarding the wiring within the 2-layer block,
A y-direction wiring track 16 between two-layer blocks will be used.

[Problem that the invention seeks to solve]

In the conventional master slice internal cell structure shown in FIGS. 3 and 4, wiring tracks in the same direction are normally set at the same pitch regardless of whether they are intrablock wiring tracks or interblock wiring tracks. Therefore, the wiring track pitch often does not reach the minimum value allowed by the design rules for each wiring layer. This will be explained using the example of the cell layout shown in FIG.

When Al wiring with a thickness of about 0.7 μm is used as the first layer wiring, the minimum wiring pitch allowed by today's lithography technology is 5 to 7 μm. On the other hand, the arrangement pitch of element electrodes such as transistors is affected by factors other than wiring design rules, such as diffusion pattern design rules, and needs to be approximately 8 μm. Therefore, in FIG. 4, the first layer x-direction intra-block wiring tracks 17 are set at a pitch of 8 μm, and since the wiring tracks in the same direction are set at the same pitch, the first layer x-direction inter-block wiring tracks 15 are set at a pitch of 8 μm. The pitch is also 8 μm. Similarly, regarding the y-direction wiring track, if Al wiring with a thickness of approximately 1.5 μm is used as the second layer wiring, the minimum allowable wiring pitch is approximately 12 μm.
In addition to the wiring track 1 in the y direction within the 1st layer block.
The arrangement pitch of 8 is also 12 μm. Therefore, the conventional wiring track structure described above increases the internal cell area and internal cell placement pitch, leading to an increase in chip size, which becomes unacceptable, especially in large-scale master slices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type semiconductor integrated circuit which does not impair the ease of wiring design of the above-mentioned layout structure and reduces the chip area.

[Means for solving problems]

The semiconductor integrated circuit of the present invention has a cell array in which a plurality of cells each consisting of a plurality of elements are arranged in rows and columns in two directions perpendicular to each other, and one or more wiring layers are used to connect one or more cells within the cell. In a master slice type semiconductor integrated circuit that connects a plurality of elements to form a circuit block and connects one or more of the circuit blocks to derive a group of integrated circuits having different functions,
Layout pitch of wiring for composing a circuit block arranged in one or more directions belonging to one or more wiring layers and a circuit block belonging to at least one or more wiring layer arranged in the same direction as the wiring for structuring the circuit block. It is constructed by making the arrangement pitches of the interlayer wirings different.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a layout diagram of a first embodiment of the present invention.

This embodiment, like the conventional example shown in FIG. 4, is an example in which the present invention is applied to an ECL type master slice, and FIG. 1 shows the layout of the internal cell array section repeating unit 7a. That is, in this embodiment, the present invention is applied to the first-layer intra-block y-direction wiring track 18 and the second-layer inter-block y-direction wiring track 16.

Y-direction wiring tracks 18 and 2 in 1-layer block
The arrangement pitches of the inter-layer block y-direction wiring tracks 16 are set to different pitches allowed by the layout design rules for each wiring layer. When wiring layers similar to those shown in the conventional example shown in FIG. 4 are used, a wiring pitch of 6 μm or more is allowed for first-layer wiring, and a wiring pitch of 12 μm or more is allowed for second-layer wiring. Therefore, in this embodiment, the x-direction arrangement pitch of the y-direction wiring tracks 18 within the first-layer block is set to 8 μm, and the x-direction arrangement pitch of the y-direction wiring tracks 16 between the second-layer blocks is set to 12 μm. y of the x-direction wiring track 17 in the 1st layer block
If the directional arrangement pitch is 8 .mu.m as in the conventional example shown in FIG. 4, all the data positions of the wiring within the one-layer block will be arranged at the block design lattice point positions of 8 .mu.m in the x direction and 8 .mu.m in the y direction. Furthermore, the first-layer intra-block y-direction wiring track 18 and the second-layer inter-block y-direction wiring track 16 are arranged so as to coincide with each other at least common multiple of 24 μm, and block terminals are placed on these matching wiring tracks. It is preferable that the

By using the wiring track arrangement structure explained above with reference to FIG. 1, intra-block wiring and block terminals are placed at preset block design lattice point positions, and block terminals are placed on inter-block wiring tracks. Therefore, it is possible to set the intra-block y-direction wiring tracks 18 densely without impairing the ease of block design and inter-block wiring design in consideration of automatic design and the like. As a result, the same number of
While securing the wiring track in the layer block in the y direction,
Cell size can be reduced.

FIG. 2 is a layout diagram of a second embodiment of the present invention.

This embodiment also has an ECL code similar to the first embodiment.
This is an example in which the present invention is applied to a type master slice, and the present invention is applied to the first-layer intra-block x-direction wiring track 17 and the first-layer inter-block x-direction wiring track 15. That is, x in the first layer block
The y-direction pitch of the directional wiring track 17 and the y-direction pitch of the first layer inter-block x-direction wiring track 15 are different. The pitch in the y direction of the x direction wiring track 17 in the first layer block is selected to be the minimum pitch allowed by the design rules for the first layer wiring electrodes of elements such as transistors, for example, 8 μm as in the conventional example shown in FIG. On the other hand, the y-direction pitch of the first-layer inter-block x-direction wiring track 15 is selected to be the minimum pitch allowed by today's photolithography technology, for example, 6 μm, without affecting the elements. Further, the x-direction pitch of the first-layer inter-block y-direction wiring track 18 is set to 8 μm, for example, as in the first embodiment. Furthermore, preferably, the arrangement pitch of the internal cells in the y direction is set to x within the first layer block.
By making the pitch a multiple of the y-direction pitch of the directional wiring track 17, not only one cell but also multiple cells, especially y
When designing a large-scale circuit block composed of a group of two or more adjacent cells in the direction, the design is performed on a block design grid point with an 8 μm pitch in the x direction and an 8 μm pitch in the y direction, just as in the case of a circuit block composed of one cell. Allow design data to be placed. Specifically, in this embodiment, the y-direction pitch of the internal cell is set to the x-direction wiring track 17 in the first layer block.
The pitch in the y direction is set to 96 μm, which is a multiple of 8 μm. Therefore, for example, if the lower left block design lattice point of the lower cell is selected as the block design origin 19, even if the y-direction pitch of the 1-layer inter-block x-direction wiring between cells is 6 μm, Therefore, all block design lattice points, including the lower and upper cells, are placed on a uniform pitch of 8 μm in the x direction and 8 μm in the y direction, so even when designing a block of 2 cells at once, the design Simplification and automation become possible. On the other hand, since the y-direction pitch of the x-direction wiring tracks 15 between 1-layer blocks is reduced to 6 μm, the same number of 1-layer inter-block x-direction wiring tracks can be secured compared to the conventional example shown in FIG. At the same time, it is possible to reduce the pitch of the internal cells in the y direction, and thus the chip size.

In the above embodiment, an example was explained in which two-layer wiring is used in a bipolar ECL type master slice, but the present invention can also be applied to other types such as CMOS type, and can also be applied to those having three or more wiring layers. Of course, it can be applied.

〔Effect of the invention〕

As explained above, in the master slice, the arrangement pitch of wiring tracks for configuring circuit blocks and the arrangement pitch of wiring tracks between circuit blocks arranged in the same direction can be adjusted to match each other as permitted by design rules. By setting different dimensions, it is possible to obtain a semiconductor integrated circuit with reduced internal cell arrangement pitch and, by extension, chip size, without sacrificing the ease of simplification and automation of circuit block design and circuit block-to-circuit block design. It has the effect of being

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a first embodiment of the present invention, FIG. 2 is a layout diagram of a second embodiment of the present invention, and FIG. 3 is a layout diagram of an example of a conventional master slice type semiconductor chip. FIG. 4 is a layout diagram of an example of an internal cell array unit repeating unit centered on one internal cell of a conventional bipolar ECL circuit master slice. 1... Chip, 2... Peripheral area, 3... Internal cell array area, 4... Internal cell, 5... Cell column,
6... Wiring area, 7a, 7b... Internal cell array unit repeating unit, 10... Transistor, 11...
Resistor, 12... Contact, 13... One-layer wiring pattern for electrode, 14... In-cell inter-element wiring area,
15...1 layer inter-block x direction wiring track, 1
6... Y-direction wiring track between two-layer blocks, 17
...x-direction wiring track in 1-layer block, 18...
...Y direction wiring track in 1st layer block, 19...
Origin for block design.

Claims (1)

[Claims] 1. A cell array in which a plurality of cells each consisting of a plurality of elements are arranged in rows and columns in two directions orthogonal to each other, and one or more wiring layers interconnect the plurality of cells in one or more cells. In a master slice type semiconductor integrated circuit, which connects two or more elements to form a circuit block, and connects one or more of the circuit blocks to derive a group of integrated circuits having different functions, the first layer 1 belonging to the above wiring layer
The arrangement pitch of the wiring for composing a circuit block that is arranged in the same direction as the wiring for composing a circuit block is different from the arrangement pitch of the wiring between circuit blocks belonging to at least one or more wiring layers that is arranged in the same direction as the wiring for structuring the circuit block. A semiconductor integrated circuit characterized by: 2. Claim 1, wherein the arrangement pitch of the cells in the direction orthogonal to the wiring for forming the circuit block is an integral multiple of the arrangement pitch of the wiring for forming the circuit block.
Semiconductor integrated circuit described in Section 1.