JPH0475665B2 - - Google Patents
Info
- Publication number
- JPH0475665B2 JPH0475665B2 JP57092915A JP9291582A JPH0475665B2 JP H0475665 B2 JPH0475665 B2 JP H0475665B2 JP 57092915 A JP57092915 A JP 57092915A JP 9291582 A JP9291582 A JP 9291582A JP H0475665 B2 JPH0475665 B2 JP H0475665B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- layer
- integrated circuit
- main line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体集積回路装置に係り、特にマ
スタースライス方式を採用した装置に関わるもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a device employing a master slice method.
マスタースライス方式の半導体集積回路装置
は、予め複数の素子からなる基本セルを半導体基
板に多数作り込んでおき、配線層並びに接続穴を
変更することにより所望の回路動作を得ようとす
るもので、新たな機能の回路の要望に対し、比較
的簡単に対処出来る特徴を有している。すなわ
ち、金属配線を形成する以前の工程により作成さ
れる半導体チツプは、全ての機能回路に共通であ
るため、上記方式を採用すると、開発期間の短
縮、製造コストの低減が図れ、多品種小量生産を
可能とする。
A master slice type semiconductor integrated circuit device is a device in which a large number of basic cells each consisting of a plurality of elements are fabricated on a semiconductor substrate in advance, and desired circuit operation is obtained by changing wiring layers and connection holes. It has the feature of being able to respond to requests for circuits with new functions relatively easily. In other words, since the semiconductor chip created through the process before forming metal wiring is common to all functional circuits, adopting the above method shortens the development period and reduces manufacturing costs, making it possible to manufacture high-mix, low-volume chips. enable production.
マスタースライス方式によるゲートアレイ型大
規模集積回路装置の一般的な例を第１図に示す。
すなわち、この半導体集積回路装置は半導体チツ
プ上が、素子領域１、配線領域２、入出力端子並
びに入出力回路領域３に分けられている。素子領
域１への電源供給は、通常、素子領域１上にVDD
とGNDとからなる配線４（第１層）を設けるこ
とによつて行なわれ、また、素子領域１の機能ブ
ロツク間の接続は配線領域２上に設けられる配線
パターン（第２層）によつて行なわれる。 FIG. 1 shows a general example of a gate array type large-scale integrated circuit device using the master slice method.
That is, in this semiconductor integrated circuit device, the semiconductor chip is divided into an element region 1, a wiring region 2, input/output terminals, and an input/output circuit region 3. The power supply to the element area 1 is normally provided by V DD on the element area 1.
This is done by providing a wiring 4 (first layer) consisting of and GND, and the connection between functional blocks in the element area 1 is made by a wiring pattern (second layer) provided on the wiring area 2. It is done.
しかし、この方式では、大規模化に伴つて、素
子領域が細長くなると電源配線の抵抗、インダク
タンスが増大し、性能低下を招く不都合があつ
た。そこで、配線層を３層とした構造も考えられ
ている。第２図に３層配線を用いたゲートアレイ
型大規模集積回路装置の電源配線の例を示し、ま
た第３図に素子領域の構造を示す。第３層の金属
を用いて、電源幹線５を設け、これを素子領域１
上の特定の場所で第１もしくは第２配線層によつ
て設けられた電源支線６に接続する。したがつ
て、素子領域１内に電源幹線５と電源支線６とを
接続する領域（電源分枝セル７と呼ぶ）を必要と
する。このため、この方式では、機能ブロツク８
を電源分枝セル７上に配置出来ず、配置の自由度
が制限され、また素子利用効率の低下を招く欠点
があつた。 However, this method has the disadvantage that as the scale increases, the resistance and inductance of the power supply wiring increases as the element area becomes narrower and narrower, resulting in a decrease in performance. Therefore, a structure with three wiring layers is also being considered. FIG. 2 shows an example of power supply wiring for a gate array type large-scale integrated circuit device using three-layer wiring, and FIG. 3 shows the structure of an element region. A power supply main line 5 is provided using the third layer of metal, and this is connected to the element area 1.
It is connected to the power supply branch line 6 provided by the first or second wiring layer at a specific location above. Therefore, a region (referred to as a power branch cell 7) for connecting the power supply main line 5 and the power supply branch line 6 is required within the element region 1. Therefore, in this method, the function block 8
cannot be arranged on the power supply branch cell 7, which limits the degree of freedom in arrangement, and also has the drawback of lowering element utilization efficiency.
本発明は、上記事情を考慮してなされたもの
で、マスタースライス方式によるゲートアレイ型
大規模集積回路に適した半導体集積回路装置を提
供することを目的としている。
The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device suitable for a gate array type large-scale integrated circuit using a master slice method.
本発明によれば、少なくとも素子領域上に電源
支線を設けるとともに上記素子領域に近接した配
線領域上に上記電源支線に接続される電源幹線を
設け、これら電源線を同一配線層で構成してい
る。また、素子領域の機能ブロツク基本セル相互
の信号端は配線領域において上記配線層とはそれ
ぞれ異なる配線層によつて接続される。
According to the present invention, a power supply branch line is provided at least on the element region, and a power supply main line connected to the power supply branch line is provided on a wiring region close to the element region, and these power supply lines are configured in the same wiring layer. . Further, the signal ends of the functional block basic cells in the element region are connected in the wiring region by wiring layers different from the above-mentioned wiring layers.
本発明によれば従来技術に比べ、下記の効果が
得られる。すなわち、配線領域上に電源幹線を設
けているため、この電源幹線を幅広く形成するこ
とができ、さらに素子領域上の電源支線に電源幹
線を複数箇所で接続しているので、電源支線の抵
抗、インダクタンスを等価的に小さくすることが
でき、性能向上を図れる。また、素子領域内に電
源分枝用セルを設けなくてよいので、機能ブロツ
ク配置の自由度が増し、素子の利用効果を向上で
きる。機能ブロツク間の相互接続のための相互配
線として、上記の各電源線よりも上層で、基板か
らの間隔が大きく静電容量の小さい配線層を使う
ため、相互配線は低容量な配線となり、信号の遅
延を少なくでき、高性能化を図れる。
According to the present invention, the following effects can be obtained compared to the conventional technology. In other words, since the power supply main line is provided on the wiring area, this power supply main line can be formed widely, and furthermore, since the power supply main line is connected to the power supply branch line on the element area at multiple points, the resistance of the power supply branch line, Inductance can be equivalently reduced, and performance can be improved. Further, since it is not necessary to provide a power branching cell within the element region, the degree of freedom in arranging functional blocks is increased, and the effect of using the element can be improved. As the mutual wiring for interconnecting functional blocks, a wiring layer with a large distance from the substrate and low capacitance is used above each power supply line, so the mutual wiring becomes a low capacitance wiring, and the signal The delay can be reduced and the performance can be improved.
第４図に本発明を適用したゲートアレイ型大規
模集積回路の例を示す。
FIG. 4 shows an example of a gate array type large-scale integrated circuit to which the present invention is applied.
素子領域１の両側に近接させて第１配線層で電
源幹線９が設けてあり、電源幹線９と素子領域１
内部の電源支線６とは、所々で第１または第２配
線層に所属する配線１４で接続されている。素子
領域１上に配置された機能ブロツク１３の入出力
端子は第２配線層を用いて素子領域１の端に引き
出されており、これらの配線領域２における配線
は第２配線層に所属する配線１０と第３配線層に
所属する配線１１と接続穴１２とによつて行なわ
れている。 A power supply main line 9 is provided in the first wiring layer in close proximity to both sides of the element region 1, and the power supply main line 9 and the element region 1 are connected to each other.
The internal power supply branch line 6 is connected at some places with wiring 14 belonging to the first or second wiring layer. The input/output terminals of the functional block 13 arranged on the element area 1 are drawn out to the edge of the element area 1 using the second wiring layer, and the wiring in these wiring areas 2 is the wiring belonging to the second wiring layer. 10, wiring 11 belonging to the third wiring layer, and connection hole 12.
したがつて、上記構成であると、電源幹線９の
幅を広くできるし、電源分枝用セルを必要としな
い。また、配線１０，１１が従来よりも上層の配
線層で行われるので、基板から配線１０，１１ま
での距離が長くなり、配線容量が減少する。従つ
て、前述した効果が得られることになる。 Therefore, with the above configuration, the width of the power main line 9 can be increased, and power branch cells are not required. Further, since the wirings 10 and 11 are formed in an upper wiring layer than in the conventional case, the distance from the substrate to the wirings 10 and 11 becomes longer, and the wiring capacitance decreases. Therefore, the above-mentioned effects can be obtained.
なお、本発明は、配線層数が３の場合に限られ
るものではなく、更に多層の場合にも適用でき
る。 Note that the present invention is not limited to the case where the number of wiring layers is three, but can also be applied to a case where the number of wiring layers is multilayered.
第１図は従来のマスタースライス方式によるゲ
ートアレイ型大規模集積回路装置の構成例を示す
図。第２図は同じく従来の３層配線を用いたゲー
トアレイ型大規模集積回路装置の構成例を示す
図。第３図は第２図に示す装置の素子領域の拡大
図。第４図は本発明の一実施例に係る半導体集積
回路装置の構成図である。
９…第１配線層で作られた電源幹線、１０…第
２配線層で作られた信号配線、１１…第３配線層
で作られた信号配線、１２…接続穴、１３…機能
ブロツク。
FIG. 1 is a diagram showing an example of the configuration of a gate array type large-scale integrated circuit device using a conventional master slice method. FIG. 2 is a diagram showing a configuration example of a gate array type large-scale integrated circuit device using conventional three-layer wiring. FIG. 3 is an enlarged view of the element area of the device shown in FIG. 2. FIG. 4 is a configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. 9...Power main line made in the first wiring layer, 10...Signal wiring made in the second wiring layer, 11...Signal wiring made in the third wiring layer, 12...Connection hole, 13...Functional block.
Claims (1)
セルを複数個配列し集積してなるチツプに必要に
応じた配線パターンを施して所望の回路動作を実
現するマスタースライス方式の半導体集積回路装
置において、 前記基本セルを配列する素子領域上に電源支線
を設けると共に、該素子領域に近接した配線領域
上に電源幹線を設け、且つ電源支線と電源幹線と
は複数箇所で接続し、 前記素子領域の基本セル間の相互配線を、上記
各電源線よりも上層の配線層で形成してなること
を特徴とする半導体集積回路装置。 ２ 前記電源支線及び電源幹線は第１層であり、
これらの各電源線を接続する配線は第１層又は第
２層であり、前記相互配線は第２層及び第３層で
あることを特徴とする特許請求の範囲第１項記載
の半導体集積回路装置。[Claims] 1. A master slicing method in which a chip is formed by arranging and integrating a plurality of basic cells each consisting of a plurality of active elements on a semiconductor substrate, and then applying wiring patterns as necessary to achieve a desired circuit operation. In the semiconductor integrated circuit device, a power supply branch line is provided on an element region in which the basic cells are arranged, a power supply main line is provided on a wiring region close to the element region, and the power supply branch line and the power supply main line are connected at a plurality of points. . A semiconductor integrated circuit device, wherein mutual wiring between basic cells in the element region is formed in a wiring layer above each of the power supply lines. 2. The power branch line and the power main line are in the first layer,
The semiconductor integrated circuit according to claim 1, wherein the wiring connecting each of these power supply lines is a first layer or a second layer, and the mutual wiring is a second layer and a third layer. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9291582A JPS58210636A (en) | 1982-05-31 | 1982-05-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9291582A JPS58210636A (en) | 1982-05-31 | 1982-05-31 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58210636A JPS58210636A (en) | 1983-12-07 |
| JPH0475665B2 true JPH0475665B2 (en) | 1992-12-01 |
Family
ID=14067775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9291582A Granted JPS58210636A (en) | 1982-05-31 | 1982-05-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58210636A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62216342A (en) * | 1986-03-18 | 1987-09-22 | Toshiba Corp | Manufacture of semiconductor integrated circuit device |
| JPH07123139B2 (en) * | 1986-03-28 | 1995-12-25 | 株式会社東芝 | Layout method of semiconductor logic integrated circuit device |
| JPH0719843B2 (en) * | 1988-09-20 | 1995-03-06 | 三洋電機株式会社 | Semiconductor integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432085A (en) * | 1977-08-16 | 1979-03-09 | Mitsubishi Electric Corp | Semiconductor intergrated circuit |
| JPS5493375A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
1982
- 1982-05-31 JP JP9291582A patent/JPS58210636A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432085A (en) * | 1977-08-16 | 1979-03-09 | Mitsubishi Electric Corp | Semiconductor intergrated circuit |
| JPS5493375A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58210636A (en) | 1983-12-07 |
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