JPS6074548A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive to integrate a semiconductor integrated circuit such as a gate array, etc., in higher density, which has adopted a master slice system, by a method wherein wiring layeres are formed more than three layers in number and the wiring of the uppermost layer is used for a connecting wiring between wiring tracks across a logical block. CONSTITUTION:Wirings 7 have been provided at the wiring region 2 of an element region 1, crossing over a wiring track 5 using a first layer metal wiring, input terminals 6 using a second layer metal wiring for the exclusive use of the X-Y direction and a logical block using a third layer metal wiring for the exclusive use of the X-Y direction. Wirings in the X-Y direction can be freely performed in the logical block by the first and second layer mtetal wirings. According to such a way, there is no necessity for using a vacant block for wiring, which crosses the element region 1, thereby enabling to significantly reduce the area of the element region 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor integrated circuit device, and particularly to a device employing a master slice method.

[Prior art and its problems]

A master slice semiconductor integrated circuit device is a device in which a large number of basic cells consisting of multiple elements are fabricated in advance on a semiconductor substrate, and the desired circuit operation is obtained by changing the wiring layers and connections. It has the feature that it can relatively easily meet the demand for circuits with various functions.

In other words, since the semiconductor chip created by the process before forming metal wiring has a common functional circuit,
If the above method is adopted, it has the advantage of shortening the development period and manufacturing cost through automatic design, and making it possible to produce a wide variety of products in small quantities. It has the disadvantage that the integration density is too low because it generates empty blocks.

FIG. 1 shows part of a large-scale integrated circuit using the master slice method, which is divided into an element area 1 and a wiring area 2. The element area has 35 logic blocks 3 and 10 empty blocks 4. When the wiring crosses the element area in this way, an empty block is prepared as in the conventional case.
In the method of wiring across this, as mentioned above,
A problem arises in that the integration density does not increase.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device suitable for a gate array large-scale integrated circuit using the master slice method.

[Summary of the invention]

The present invention is characterized in that when wiring connecting logic block terminals traverses the cable region, the uppermost layer is used.

〔Effect of the invention〕

According to this invention, there is no need to prepare an empty block for wiring in the element area, and it is possible to traverse any logic block.As a result, the area occupied by the element area is reduced, and the wiring can be used for gate arrays, etc. High-density integration of integrated circuits can be achieved.

[Embodiments of the invention]

An embodiment in which the present invention is applied to a master slice type gate array is shown in FIG. 2 corresponding to FIG. - Logic blocks consisting of MOS cells are arranged in columns, and in the wiring area 2 there are wiring tracks 5,X using first layer metal wiring.

Input terminal 6, X using direction-specific second layer metal wiring
A wire 7 is provided which traverses the logic block using direction-specific third layer metal wire.

In some cases, it is possible to provide the wiring using second layer wiring, such as the wiring 8 that crosses over the logic block.

Inside the logic block, wiring in the X1Y directions is freely provided by first and second layer metal wiring. The input terminal 6 using the second layer metal wiring is an extension of the wiring within the logic block or a wiring led out from a contact hole provided in the logic block.

According to this embodiment, there is no need to use empty blocks for wiring that crosses the element area, and as is clear from a comparison with FIG. 1, 10 empty blocks are required out of 45 blocks in the element area. Instead, the element area can be created with only 35 logic blocks, and the area of the conventional element area can be significantly reduced.

Note that the wiring layer is not limited to three layers, and a metal wiring layer is further provided under the first layer metal wiring layer that forms the wiring track, and this layer is used as a layer exclusively for VD8 that traverses the cell rows.
It can also be used as a layer.

[Brief explanation of drawings]

FIG. 1 is a plan view of a gate of a conventional master slice method. In the figure, 1... Element area, 2... Wiring area, 3... Logic program, 4... Empty block, 5... Wiring track, 6... Input/output terminal, 7... ... Wiring that crosses over the logical block using the top layer, 8... Wiring that crosses over the logical block using the second layer. Agent: Patent attorney Kensuke Chika (and 1 other person)

Claims (2)

[Claims] (1) In a semiconductor integrated circuit in which logic blocks are arranged in a matrix and wiring tracks are provided between the logic blocks, the number of wiring layers is three or more, and the wiring on the top layer is routed across the logic blocks between the wiring tracks. A semiconductor integrated circuit characterized in that it can be used for connection wiring. (2) The number of wiring layers is three, the first and second wiring layers are used for wiring within the logic block, the first and second wiring layers are used for the wiring track, and the logic 2. The semiconductor integrated circuit according to claim 1, wherein a third wiring layer is used for wiring that crosses over the block.