JPS59155145A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a large-scale integrated circuit device according to a master slice system by a method wherein fundamental cell rows, in which longitudinally arranged fundamental cells have been rotated at a right angle, are individually provided at the upper and lower parts of the element region in a gate array type large-scale integrated circuit. CONSTITUTION:Fundamental cell rows 1a and 1b, in which longitudinally arranged fundamental cells have been rotated at a right angle, are provided on the upside and downside of the element region and wirings between each of the input and output terminals on the upside and downside of the chip and the element region are performed, centering around the 1a and the 1b. In brief, the fundamental cells to be connected to the input and output terminals on the upside and downside of the chip are arranged as close as possible to the 1a and the 1b. Fundamental cell rows 1 other than the above-mentioned fundamental cell rows are arranged at regular intervals in the lateral direction. According to such the arrangement and constitution of the element region, the area of the wiring regions between each of the upside and downside of the chip and the element region can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor integrated circuit device, and particularly to a device employing a master slice method.

[Prior art and its problems]

A master slice type semiconductor integrated circuit device is a basic cell consisting of multiple elements in advance! It attempts to obtain the desired circuit operation by fabricating a large number of circuits on a semiconductor substrate and changing the wiring layers and connection holes, and has the feature that it can relatively easily respond to requests for circuits with new functions. are doing.

In other words, since the semiconductor chip created by the process before forming metal wiring is common to all functional circuits, adopting the above method shortens the development period, reduces manufacturing costs, and allows for high-mix, low-volume production. enable production.

A general example of a gate array type large-scale integrated circuit device using the master slice method is shown in Figure 1.

That is, in this semiconductor integrated circuit device, the semiconductor chip is divided into an element region 1, a wiring region 2, input/output terminals, and an input/output circuit region 3. Further, the wiring is usually performed using two-layer metal wiring, and separate layers are assigned to horizontal (horizontal) and vertical (vertical) directions, respectively. moreover,
The element region is composed of several rows of basic cells arranged in the vertical direction at equal intervals (two units) in the horizontal direction.

However, in this method, when the number of wires between the element region and the input/output terminal increases as the scale increases, the area of the wire region increases, resulting in a reduction in the degree of integration of the chip.

In particular, when wiring between the element area and the input/output terminals on the top and bottom sides of the chip, the wiring area is also used for the above wiring.
Furthermore, since it is also used for wiring between element regions, the area of the wiring region inevitably increases, and at the same time, the degree of congestion of the wiring also increases.

Furthermore, when a chip is divided into several rectangular blocks as shown in Fig. 2 and so-called hierarchical placement and wiring are performed, the wiring area is Since it is used for wiring between upper and lower rectangular blocks, there is a problem in that the number of tracks in the vertical direction increases.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and has a gate array type input scale V! The purpose is to provide integrated circuit devices).

[Summary of the invention]

The gist of the present invention is to provide basic cell rows in which basic cells are arranged vertically (i.e., rotated at right angles), and to place them above and below the element area of the gate array type large-scale integrated circuit shown in FIG. The device region is arranged and configured by arranging one of each.

〔Effect of the invention〕

According to the present invention, the arrangement configuration of the conventional element region (compared with two
The following effects can be obtained. In other words, by arranging the basic cells arranged vertically at right angles and rotating the basic cell rows, one each on the top and bottom of the element area, the input/output terminals and the element area on the top side and F side of the chip are arranged. This can be done by effectively using vertical tracks.

For example, according to the present invention, the wiring between the input/output terminals and the element area as shown in FIG. 3 is implemented as shown in FIG. 4, eliminating horizontal wiring and vertical wiring. The level of congestion will also decrease. As a result, the area of the wiring region is reduced, making it possible to increase the degree of integration of the chip. Furthermore, when the chip is divided into several rectangular blocks (-1), the basic cell rows described above are placed on the boundaries of the vertically adjacent rectangular JT6 blocks.
By arranging them together, it is possible to significantly reduce the number of tracks in the vertical direction between rectangular blocks by C2, and as a result, both the area and the degree of congestion of the wiring area are reduced.

[Embodiments of the invention]

FIGS. 5 and 6 show examples of gate array type large-scale integrated circuits to which the present invention is applied. Basically, it is assumed to be of 0MO8 type consisting of a plurality of active elements, for example.

In FIG. 5, basic cell rows 1a*1b, which are basic cells arranged vertically and rotated at right angles, are provided on the upper and lower sides of the element area, and the input/output terminals ( The wiring between the (pad) and the element area is performed mainly on la and lb. In other words, the basic cells that connect the input/output terminals C on the top and bottom sides of the chip are connected as much as possible.
Place it at t 1 b. Otherwise, as shown in the figure, the basic cell rows l are arranged at equal intervals (two horizontally). By arranging and configuring the element regions in this way, the upper and lower sides of the chip are The area of wiring regions between device regions is reduced.

In addition, FIG. 6 is divided into four rectangular blocks of steps A, B, C, and D, and the above-mentioned basic cell rows Ai, Bi, Ci, Di (i = 1.2) are placed on the upper and lower sides of each block.
The arrangement of the element region is shown. Here, A
The wiring between and C is implemented using the wiring area between A2 and 01 by arranging basic cells in a connection relationship between A2 and CI as much as possible. Wiring between B and D is also carried out in the same way. This makes it possible to reduce the number of tracks in the vertical direction of each block, and the area and degree of congestion of the wiring area are both reduced by C2.

[Brief explanation of the drawing]

Figure 1 is a plan view showing an example of the configuration of a gate array type large-scale integrated circuit device using the conventional master slice method, and Figure 2 is the same. 3 and 4 are plan views showing detailed explanations of the present invention, and FIGS. 5 and 886 are plan views showing configuration examples of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. Agent: Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a master slice type semiconductor integrated circuit device, in which a chip is made by arranging and integrating a plurality of basic cells on a semiconductor substrate, the basic cells are arranged vertically, and a desired circuit operation is realized by applying wiring patterns as necessary. A row of cells arranged side by side and a row of cells rotated at right angles are provided, and the latter cell row is arranged at least one each at the top and bottom of the element area of the chip, and the former cell row is arranged in the area of other elements. 1. A semiconductor integrated circuit device, characterized in that an element region is arranged horizontally in a region. (2) A patented circuit device characterized in that when a chip is divided into rectangular blocks and hierarchical arrangement and wiring are performed, rotating cell rows are also provided in adjacent areas of each upper and lower block.