JPS61139044A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize the increase in area occupied by wiring regions of a chip even if the chip is made in a larger size, by composing cell columns in the central portion of the chip, of basic cells provided with one or more regions to be passed through by a wiring layer. CONSTITUTION:A chip is wired with two metal wiring layers on condition that an element region 1 and a wiring region are wired with the first and second metal layers while the first metal layer is used in the longitudinal (vertical) direction and the second metal layer is used in the transverse (horizontal) direction. Two types of basic cells 4, namely the basic cells having one or more regions to be passed through by the second metal layer and the basic cells having less such regions are prepared. For defining an element region 1, one or more columns of cells in the central portion of the chip are composed of the former type of basic cells arranged vertically while one or more columns in the right-hand and left-hand portions of the chip are composed of the latter type of cells arranged vertically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a device employing a master slice method.

[Technical background of the invention and its problems]

A master slice type semiconductor integrated circuit device is a device in which a large number of basic cells each consisting of a plurality of elements are fabricated on a semiconductor substrate in advance, and desired circuit operation is obtained by changing wiring layers and connection holes. It has the feature of being able to respond to requests for circuits with new functions relatively easily.

In other words, since the semiconductor chip created by the process before forming metal wiring is common to all functional circuits, adopting the above method can shorten the development period and reduce manufacturing costs, allowing for high-mix, low-volume production. is possible.

FIG. 4 shows a general example of a gate array type large-scale integrated circuit device using the master slice method.

That is, in this semiconductor integrated circuit device, the top of the semiconductor chip is divided into an element region 1, a wiring region 2, input/output terminals, and an input/output circuit region 3.

In addition, wiring is usually performed using two-layer metal wiring, with separate layers being allocated to horizontal (horizontal) and vertical (vertical) wiring. Further, the element region is constructed by arranging basic cells in the vertical direction in several rows at equal intervals in the horizontal direction.

Further, a logic gate is realized by applying a wiring pattern to realize a desired operation to one or more basic cells arranged vertically.

However, in this method, when the number of wires between element regions increases as the scale increases, the area of the wire regions increases, leading to a decrease in the degree of integration of the chip. In particular, as the scale increases, passing wiring that crosses several cell columns becomes a problem, and as the scale increases, the number of passing wiring increases.

Further, in general, passing wiring tends to be concentrated in cell rows near the center of the chip. Pass-through wiring is possible only at locations in the logic gate where there is no metal wiring pattern of a layer used for lateral (horizontal) wiring. Therefore.

The locations where passing wiring is possible vary depending on each logic gate, and when implementing passing routing that crosses multiple cell columns, the locations where five passing routings are possible are searched for each cell column.
Pass-through wiring does not run straight, but often has a staircase-like pattern. As a result, the area of the wiring region increases, resulting in a disadvantage that the degree of integration of the chip decreases.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances.

The purpose of this invention is to provide a gate array type large-scale integrated circuit device using a master slice method.

[Summary of the invention]

The gist of the present invention is to conduct the wiring with two-layer metal wiring, and 1.2
The basic condition is that the element area and wiring area are wired using the metal of the first layer, and that the metal of the first layer is used vertically (vertically) and the metal of the second layer is used horizontally (horizontally). As a cell, one or more areas are secured for the second layer metal passing wiring.

Two types of cells with fewer locations in the same area are prepared, and when configuring the element area, one or more cell rows in the center of the chip are formed by vertically connecting the former of the two types of basic cells described above. Arrange them side by side, one each for the right and left parts of the chip.
Two or more cell rows are formed by vertically arranging the latter basic cells. Furthermore, in realizing logic gates, we prepared two types: the former, which consists of basic cells arranged vertically, and the latter, which consists of basic cells arranged vertically. When realizing a passing wiring for a cell column in which gates are arranged, a straight passing wiring without a stepped shape is realized by using a place for the passing wiring secured in advance in a basic cell.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained compared to the configuration method of a gate array type large-scale integrated circuit using the conventional master slice method.

In other words, since the cell row in the central part of the chip, where passing wiring is generally concentrated, is composed of basic cells that have secured one or more areas for passing wiring, two or more consecutive cell rows in this part When realizing a passing wiring that crosses the
By using this area of the basic cell, passing wiring can be realized at the same position (y coordinate) for each cell column, and step-like wiring within the wiring area is not required. As a result, the degree of congestion of wiring within the wiring area is effectively alleviated, and even when the scale is increased, it is possible to reduce the rate of increase in the area of the wiring area compared to the conventional method, and it is possible to increase the density of the chip. results in an increase in

In addition, since a cell row is made up of basic cells that have an area reserved for one-pass wiring, the number of basic cells that can be placed in one cell row is reduced, but two types of basic cells with different locations in the above area are prepared. On the left and right sides of the chip, the number of basic cells in the entire device area is reduced because the number of basic cells in the entire device area is reduced because the number of areas for passing wiring is smaller (some have no such area at all) to form cell rows. The above-mentioned effect of improving the degree of integration can be obtained without unnecessarily reducing the amount of data.

Furthermore, when determining the position of a passing route that crosses two or more consecutive cell rows, it is no longer necessary to search for a passable area for each cell row, making automatic routing tools easier. realizable.

[Embodiments of the invention]

FIG. 1 shows an example of a gate array type large-scale integrated circuit using the master slice method to which the present invention is applied.

The basic cell is 1, for example, a CMO8 consisting of multiple active elements.
Make it into a mold. In Figure 1, 3 each on the right and left sides of the chip.
One cell column is made up of basic cells for which no area is secured for passing wiring, and the other cell columns are made up of basic cells having one area for passing wiring. FIG. 2 shows the structure of the two types of basic cells used in FIG. 1.

FIG. 3 shows an example of implementing the through wiring, which is a feature of the present invention, in comparison with a conventional example. As shown in FIG. 3, according to the present invention, the passing wiring positions can be obtained at the same y coordinate, so that step-like wiring as in the conventional example is not necessary.

5. The present invention is not limited to the above embodiments,
Various modifications can be made without departing from the spirit of the invention. For example, in FIG. 1, each of the three cell rows on the right and left sides of the chip is a basic cell with one area for passing wiring, and the other cell rows have two areas above and below the basic cell. It may be formed from a basic cell having two locations (or two locations at one end).

In addition to this method of using a cell row as a unit, there is also a method in which the basic cells are changed between the central part and the upper and lower parts of the cell row, and the central area has one area exclusively for wiring. A basic cell without a wiring-dedicated area on the upper and lower sides of the cell (or two wiring-dedicated areas on the central area and one wiring-only area on the upper and lower sides) may be used.

Alternatively, the area indicated by the broken line in FIG. 1 (indicated by Al) may be configured with basic cells that have wiring dedicated areas, one each on the top and bottom of the basic cell, or two on the top or bottom of the basic cell to create a hierarchical structure. You can also use it as

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows one in which no area is secured for passing wiring, which is a feature of the present invention, and one in which one area is secured. Figure 3 is a plan view showing the shapes of the two types of basic cells that have been used, and shows a comparison between a conventional method and one in which "pass-through wiring" is realized using the region for through-wiring, which is a feature of the present invention. FIG. 4 is a plan view showing an example of the configuration of a gate array type large-scale integrated circuit device using the conventional master slice method. In the figure, 1...element area% 2...wiring area ,
3... Input/output terminal and input/output circuit area, 4... Basic cell 15... Area for passing wiring. Agent: Patent Attorney Noriyuki Chika (and 1 other person) No. 1
Figure 2 (Kyu) Figure 3 Cαλ

Claims (1)

[Claims] In a master slice type semiconductor integrated circuit device in which a desired circuit operation is realized by applying wiring patterns as necessary to a chip formed by arranging and integrating a plurality of cell rows consisting of basic cells equipped with active elements on a semiconductor substrate. , at least two types of basic cells are provided as the basic cell, a basic cell having a dedicated area for passing wiring, and a basic cell having a dedicated area for passing wiring that is smaller than the basic cell or not provided, and the former basic cell is placed in the center of the chip. A semiconductor integrated circuit device characterized by being designed to concentrate.