JPS646049U - - Google Patents
Info
- Publication number
- JPS646049U JPS646049U JP10110487U JP10110487U JPS646049U JP S646049 U JPS646049 U JP S646049U JP 10110487 U JP10110487 U JP 10110487U JP 10110487 U JP10110487 U JP 10110487U JP S646049 U JPS646049 U JP S646049U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- gate array
- integrated circuit
- cell
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000149 penetrating effect Effects 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例によるゲートアレ
イ方式の集積回路のセルを示した図であり、ａは
レイアウト図、ｂは論理回路図である。第２図は
この考案を用いて配線を実施したゲートアレイ方
式の集積回路の配線例である。第３図は従来のゲ
ートアレイ方式の集積回路のセルを示した図で、
ａはレイアウト図、ｂは論理回路図、第４図は従
来のゲートアレイ方式の集積回路の配線例である
。
１は入力Ａ、２は入力Ｂ、３は入力Ｃ、４は出
力Ｙ、５は入力Ｄ、６は出力Ｚ、７はＰ型拡散、
８はＮ型拡散、９はポリシリコン、１０は第１ア
ルミ配線、１１は第２アルミ配線、１２はコンタ
クト、１３はスルーホール、１４は第１アルミ電
源配線、１５は第１アルミ接地配線、１６はセル
、１７は縦方向配線領域、１８は横方向配線領域
、１９は貫通用第２アルミ配線。なお、図中、同
一符号は同一、又は相当部分を示す。
FIG. 1 is a diagram showing a cell of a gate array type integrated circuit according to an embodiment of this invention, in which a is a layout diagram and b is a logic circuit diagram. FIG. 2 shows an example of wiring of a gate array type integrated circuit in which wiring is implemented using this invention. Figure 3 shows a cell of a conventional gate array type integrated circuit.
A is a layout diagram, b is a logic circuit diagram, and FIG. 4 is an example of wiring of a conventional gate array type integrated circuit. 1 is input A, 2 is input B, 3 is input C, 4 is output Y, 5 is input D, 6 is output Z, 7 is P-type spreading,
8 is an N-type diffusion, 9 is polysilicon, 10 is a first aluminum wiring, 11 is a second aluminum wiring, 12 is a contact, 13 is a through hole, 14 is a first aluminum power wiring, 15 is a first aluminum ground wiring, 16 is a cell, 17 is a vertical wiring region, 18 is a horizontal wiring region, and 19 is a second aluminum wiring for penetration. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
の配置領域と配線領域を備え、配置領域にセルを
配置し配線領域を用いて各セルを相互配線するゲ
ートアレイ方式の集積回路において、配置領域を
貫通配線し効率的に配線できることを特徴とする
ゲートアレイ方式の集積回路。 Internal logic circuit block (hereinafter referred to as cell)
A gate array type integrated circuit comprising a placement area and a wiring area, in which cells are placed in the placement area and each cell is mutually interconnected using the wiring area, characterized in that wiring can be efficiently performed by penetrating the placement area. A gate array integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110487U JPS646049U (en) | 1987-07-01 | 1987-07-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110487U JPS646049U (en) | 1987-07-01 | 1987-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS646049U true JPS646049U (en) | 1989-01-13 |
Family
ID=31329790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10110487U Pending JPS646049U (en) | 1987-07-01 | 1987-07-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS646049U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139044A (en) * | 1984-12-12 | 1986-06-26 | Toshiba Corp | Semiconductor integrated circuit device |
-
1987
- 1987-07-01 JP JP10110487U patent/JPS646049U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139044A (en) * | 1984-12-12 | 1986-06-26 | Toshiba Corp | Semiconductor integrated circuit device |
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