JPH0273746U - - Google Patents

Info

Publication number
JPH0273746U
JPH0273746U JP15370188U JP15370188U JPH0273746U JP H0273746 U JPH0273746 U JP H0273746U JP 15370188 U JP15370188 U JP 15370188U JP 15370188 U JP15370188 U JP 15370188U JP H0273746 U JPH0273746 U JP H0273746U
Authority
JP
Japan
Prior art keywords
integrated circuit
conductive material
circuit chips
semiconductor device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15370188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15370188U priority Critical patent/JPH0273746U/ja
Publication of JPH0273746U publication Critical patent/JPH0273746U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例を示す断面図で
ある。第2図は本考案の第2の実施例を示す断面
図である。
FIG. 1 is a sectional view showing a first embodiment of the present invention. FIG. 2 is a sectional view showing a second embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つの基板の上に半導体集積回路のチツプを複
数個置き、相互を導電性物質で接続し、又、同一
基板の裏側に他の機能を持つ半導体集積回路のチ
ツプを複数個置き、導電性物質で接続し、一つの
ケースに収める構造をした事を特徴とする半導体
装置。
A plurality of semiconductor integrated circuit chips are placed on one substrate and connected to each other with a conductive material, and a plurality of semiconductor integrated circuit chips with other functions are placed on the back side of the same substrate and connected with a conductive material. A semiconductor device characterized by a structure in which the semiconductor device is connected to each other and housed in a single case.
JP15370188U 1988-11-25 1988-11-25 Pending JPH0273746U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15370188U JPH0273746U (en) 1988-11-25 1988-11-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15370188U JPH0273746U (en) 1988-11-25 1988-11-25

Publications (1)

Publication Number Publication Date
JPH0273746U true JPH0273746U (en) 1990-06-05

Family

ID=31429778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15370188U Pending JPH0273746U (en) 1988-11-25 1988-11-25

Country Status (1)

Country Link
JP (1) JPH0273746U (en)

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