JPH01112060U - - Google Patents
Info
- Publication number
- JPH01112060U JPH01112060U JP615588U JP615588U JPH01112060U JP H01112060 U JPH01112060 U JP H01112060U JP 615588 U JP615588 U JP 615588U JP 615588 U JP615588 U JP 615588U JP H01112060 U JPH01112060 U JP H01112060U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- ground
- layer
- ground layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の第１実施例の構成図、第２図
は本考案の第２実施例の構成図である。
FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a block diagram of a second embodiment of the present invention.
Claims (1)
ース層２を形成して該アース層をアース端子ＶＳ
Ｓに接続し、また入力端子ＩＮを入力抵抗Ｒを通
して内部回路に接続した集積回路において、該ア
ース層表面に該基板と同一導電型の半導体層４を
形成して該入力端子ＩＮを該半導体層４にも接続
してなることを特徴とする集積回路。 A ground layer 2 of an opposite conductivity type is formed on the surface of a semiconductor substrate 1 of one conductivity type, and the ground layer is connected to a ground terminal VS.
In an integrated circuit in which the input terminal IN is connected to the internal circuit through the input resistor R, a semiconductor layer 4 of the same conductivity type as the substrate is formed on the surface of the ground layer, and the input terminal IN is connected to the semiconductor layer. An integrated circuit characterized in that it is also connected to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP615588U JPH01112060U (en) | 1988-01-21 | 1988-01-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP615588U JPH01112060U (en) | 1988-01-21 | 1988-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01112060U true JPH01112060U (en) | 1989-07-27 |
Family
ID=31210146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP615588U Pending JPH01112060U (en) | 1988-01-21 | 1988-01-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01112060U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175397A (en) * | 2003-12-15 | 2005-06-30 | Matsushita Electric Ind Co Ltd | Semiconductor protector |
-
1988
- 1988-01-21 JP JP615588U patent/JPH01112060U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175397A (en) * | 2003-12-15 | 2005-06-30 | Matsushita Electric Ind Co Ltd | Semiconductor protector |
| JP4514443B2 (en) * | 2003-12-15 | 2010-07-28 | パナソニック株式会社 | Semiconductor protection device |
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