JPH0284330U - - Google Patents
Info
- Publication number
- JPH0284330U JPH0284330U JP16335688U JP16335688U JPH0284330U JP H0284330 U JPH0284330 U JP H0284330U JP 16335688 U JP16335688 U JP 16335688U JP 16335688 U JP16335688 U JP 16335688U JP H0284330 U JPH0284330 U JP H0284330U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- power supply
- semiconductor
- ground
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Description
第１図ａとｂは本考案の一実施例を示す要部平
面図、第２図は従来の半導体実装装置の構成例を
示す要部平面図である。
図において、１は半導体装置、３は信号パター
ン、４は電源パターン、５は接地パターン、１０
は電源ライン、１１は分離線、１５は接地ライン
、１９は送り孔、２０はテープ基材、をそれぞれ
示す。
1A and 1B are plan views of essential parts showing an embodiment of the present invention, and FIG. 2 is a plan view of main parts showing an example of the configuration of a conventional semiconductor mounting device. In the figure, 1 is a semiconductor device, 3 is a signal pattern, 4 is a power supply pattern, 5 is a ground pattern, 10
11 is a power supply line, 11 is a separation line, 15 is a ground line, 19 is a feed hole, and 20 is a tape base material, respectively.
Claims (1)
出力端子対応に設けられた信号パターン３と電源
パターン４と接地パターン５とを一枚のテープ基
材２０上に装備してなる半導体実装装置であつて
、 前記各半導体装置１の電源パターン４および接
地パターン５に対してそれぞれ並列に接続された
電源ライン１０と接地ライン１５とを前記テープ
基材２０上に装備してなることを特徴とする半導
体実装装置。[Claims for Utility Model Registration] A plurality of semiconductor devices 1, a signal pattern 3, a power supply pattern 4, and a ground pattern 5 provided corresponding to the input/output terminals of the semiconductor devices 1 are arranged on a single tape base material 20. The semiconductor mounting device is equipped with a power supply line 10 and a ground line 15 connected in parallel to the power supply pattern 4 and the ground pattern 5 of each semiconductor device 1, respectively, on the tape base material 20. A semiconductor mounting device characterized by being equipped with:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16335688U JPH0284330U (en) | 1988-12-15 | 1988-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16335688U JPH0284330U (en) | 1988-12-15 | 1988-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284330U true JPH0284330U (en) | 1990-06-29 |
Family
ID=31448010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16335688U Pending JPH0284330U (en) | 1988-12-15 | 1988-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284330U (en) |
-
1988
- 1988-12-15 JP JP16335688U patent/JPH0284330U/ja active Pending