JPH0158943U - - Google Patents

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Publication number
JPH0158943U
JPH0158943U JP15383887U JP15383887U JPH0158943U JP H0158943 U JPH0158943 U JP H0158943U JP 15383887 U JP15383887 U JP 15383887U JP 15383887 U JP15383887 U JP 15383887U JP H0158943 U JPH0158943 U JP H0158943U
Authority
JP
Japan
Prior art keywords
cells
type integrated
cell type
standard cell
gate array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15383887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15383887U priority Critical patent/JPH0158943U/ja
Publication of JPH0158943U publication Critical patent/JPH0158943U/ja
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のスタンダードセル式集積回路
のチツプ構造図、第2図は既存のゲートアレイの
チツプ構造図である。 1,3……パツド、2……機能セル、4……基
本セル、5……基本セル列。
FIG. 1 is a chip structure diagram of a standard cell type integrated circuit according to the present invention, and FIG. 2 is a chip structure diagram of an existing gate array. 1, 3...Pad, 2...Functional cell, 4...Basic cell, 5...Basic cell string.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一定のNOTゲートやフリツプ・フロツプなど
の機能セルを所望の機能及び特性に合せて配置し
、セル領域間に設けた配線領域を使つてセル間を
つなぐスタンダードセル式集積回路において、動
作試験用パツドを既存のゲートアレイのパツドに
対応させて行列状に配列したことを特徴とするス
タンダードセル式集積回路。
In standard cell type integrated circuits, functional cells such as certain NOT gates and flip-flops are arranged according to the desired function and characteristics, and the cells are connected using the wiring area provided between the cell areas. A standard cell type integrated circuit characterized in that the cells are arranged in rows and columns in correspondence with the pads of an existing gate array.
JP15383887U 1987-10-07 1987-10-07 Pending JPH0158943U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15383887U JPH0158943U (en) 1987-10-07 1987-10-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15383887U JPH0158943U (en) 1987-10-07 1987-10-07

Publications (1)

Publication Number Publication Date
JPH0158943U true JPH0158943U (en) 1989-04-13

Family

ID=31430029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15383887U Pending JPH0158943U (en) 1987-10-07 1987-10-07

Country Status (1)

Country Link
JP (1) JPH0158943U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240650A (en) * 1985-04-18 1986-10-25 Toshiba Corp Manufacture of semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240650A (en) * 1985-04-18 1986-10-25 Toshiba Corp Manufacture of semiconductor integrated circuit

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