JPS587300U - semiconductor integrated circuit - Google Patents

semiconductor integrated circuit

Info

Publication number
JPS587300U
JPS587300U JP9851581U JP9851581U JPS587300U JP S587300 U JPS587300 U JP S587300U JP 9851581 U JP9851581 U JP 9851581U JP 9851581 U JP9851581 U JP 9851581U JP S587300 U JPS587300 U JP S587300U
Authority
JP
Japan
Prior art keywords
circuit
semiconductor integrated
integrated circuit
gate circuit
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9851581U
Other languages
Japanese (ja)
Inventor
湊 修
敏夫 佐々木
増原 利明
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP9851581U priority Critical patent/JPS587300U/en
Publication of JPS587300U publication Critical patent/JPS587300U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はプログラム素子の構成を示す図、第2図は従来
のプログラム可能な半導体メモリ集積回路の構成を示す
略回路図、第3図は本考案の実施例を示す略回路図であ
る。 338.339・・・デコーダ、304・・・メモリセ
ルアレー、305・・・予備メモリセルアレー、306
・・・ゲート回路、307・・・予備ゲート回路、30
8・・・切替え回路。
FIG. 1 is a diagram showing the structure of a program element, FIG. 2 is a schematic circuit diagram showing the structure of a conventional programmable semiconductor memory integrated circuit, and FIG. 3 is a schematic circuit diagram showing an embodiment of the present invention. 338.339...Decoder, 304...Memory cell array, 305...Spare memory cell array, 306
... Gate circuit, 307 ... Reserve gate circuit, 30
8...Switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリセルアレー、該メモリセルアレーの選択を行なう
ゲート回路、該ゲート回路に選択信号を伝えるデコーダ
回路を有する半導体集積回路において、予備メモリセル
アレー、予備ゲート回路を設け、さらにゲート回路とデ
コーダ回路の間に切替え回路が設けられ、該切替え回路
により所望のゲート回路を予備ゲート回路に置き換える
ことができることを特徴とする半導体集積回路。  −
In a semiconductor integrated circuit that has a memory cell array, a gate circuit that selects the memory cell array, and a decoder circuit that transmits a selection signal to the gate circuit, a spare memory cell array and a spare gate circuit are provided, and a gate circuit and a decoder circuit are provided. 1. A semiconductor integrated circuit, characterized in that a switching circuit is provided between the circuits, and a desired gate circuit can be replaced with a spare gate circuit by the switching circuit. −
JP9851581U 1981-07-03 1981-07-03 semiconductor integrated circuit Pending JPS587300U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9851581U JPS587300U (en) 1981-07-03 1981-07-03 semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9851581U JPS587300U (en) 1981-07-03 1981-07-03 semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS587300U true JPS587300U (en) 1983-01-18

Family

ID=29893274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9851581U Pending JPS587300U (en) 1981-07-03 1981-07-03 semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS587300U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177797A (en) * 1983-03-28 1984-10-08 Fujitsu Ltd Semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177797A (en) * 1983-03-28 1984-10-08 Fujitsu Ltd Semiconductor memory

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