JPS6311865U - - Google Patents
Info
- Publication number
- JPS6311865U JPS6311865U JP10612686U JP10612686U JPS6311865U JP S6311865 U JPS6311865 U JP S6311865U JP 10612686 U JP10612686 U JP 10612686U JP 10612686 U JP10612686 U JP 10612686U JP S6311865 U JPS6311865 U JP S6311865U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- semiconductor memory
- output
- input
- terminal array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000014759 maintenance of location Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Credit Cards Or The Like (AREA)
Description
第１図は、本考案のブロツク図。第２図は、本
考案の制御回路の一実施例の回路図。第３図は、
本考案の制御回路の一実施例の回路図。第４図は
、本考案制御回路の一実施例の回路図。第５図は
、従来のメモリカードのブロツク図。
１は、読み書き可能な半導体メモリ、２は、電
池、３は、入出力端子列、４は、アドレスバス、
５は、データバス、６は、出力制御信号、７は、
書き込み制御信号、８は、カード制御信号、９は
、制御回路、１０は、出力制御信号、１１は、書
き込み制御信号、１２は、ダイオード、１３は、
インバータ、１４はナンドゲート、１５は、抵抗
。
Figure 1 is a block diagram of the present invention. FIG. 2 is a circuit diagram of one embodiment of the control circuit of the present invention. Figure 3 shows
FIG. 1 is a circuit diagram of an embodiment of the control circuit of the present invention. FIG. 4 is a circuit diagram of one embodiment of the control circuit of the present invention. FIG. 5 is a block diagram of a conventional memory card. 1 is a readable/writable semiconductor memory, 2 is a battery, 3 is an input/output terminal array, 4 is an address bus,
5 is a data bus, 6 is an output control signal, 7 is
8 is a card control signal; 9 is a control circuit; 10 is an output control signal; 11 is a write control signal; 12 is a diode; 13 is a
Inverter, 14 is a NAND gate, and 15 is a resistor.
Claims (1)
タ保持用電源と入出力信号用端子列を有し、前記
入出力信号用端子列からの出力制御信号と書き込
み制御信号が共に動作可能レベルの時には、前記
半導体メモリへの書き込み制御信号は動作不可能
レベルを出力する制御回路を有することを特徴と
するメモリカード。 It has at least a readable/writable semiconductor memory, a power supply for data retention, and a terminal array for input/output signals, and when both an output control signal and a write control signal from the input/output signal terminal array are at an operable level, the semiconductor memory is transferred to the semiconductor memory. A memory card comprising a control circuit that outputs a write control signal at an inoperable level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10612686U JPH0529898Y2 (en) | 1986-07-10 | 1986-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10612686U JPH0529898Y2 (en) | 1986-07-10 | 1986-07-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6311865U true JPS6311865U (en) | 1988-01-26 |
| JPH0529898Y2 JPH0529898Y2 (en) | 1993-07-30 |
Family
ID=30981202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10612686U Expired - Lifetime JPH0529898Y2 (en) | 1986-07-10 | 1986-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529898Y2 (en) |
-
1986
- 1986-07-10 JP JP10612686U patent/JPH0529898Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0529898Y2 (en) | 1993-07-30 |
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