JPS6392971U - - Google Patents
Info
- Publication number
- JPS6392971U JPS6392971U JP18962586U JP18962586U JPS6392971U JP S6392971 U JPS6392971 U JP S6392971U JP 18962586 U JP18962586 U JP 18962586U JP 18962586 U JP18962586 U JP 18962586U JP S6392971 U JPS6392971 U JP S6392971U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- memories
- data
- alternately
- switching circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Description
第１図は本考案の一実施例のブロツク図である
。
１……第一のマイクロプロセツサ、２……第二
のマイクロプロセツサ、３……第一のメモリ、４
……第二のメモリ、５……バス切り換え回路、６
……外部出力ポート。
FIG. 1 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...First microprocessor, 2...Second microprocessor, 3...First memory, 4
...Second memory, 5...Bus switching circuit, 6
...External output port.
Claims (1)
込む第一のマイクロプロセツサと、第二および第
一のメモリから交互にデータを読み出し外部ポー
トへ出力する第二のマイクロプロセツサと、前記
第一のマイクロプロセツサより前記第一および第
二のメモリを前記第一および第二のマイクロプロ
プロツサ間で排他的に動作させるバス切り換え回
路とを有することを特徴とするデータ転送装置。 a first microprocessor that alternately writes data to the first and second memories; a second microprocessor that alternately reads data from the second and first memories and outputs the data to an external port; a bus switching circuit for causing a microprocessor to operate the first and second memories exclusively between the first and second microprocessors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18962586U JPS6392971U (en) | 1986-12-08 | 1986-12-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18962586U JPS6392971U (en) | 1986-12-08 | 1986-12-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392971U true JPS6392971U (en) | 1988-06-15 |
Family
ID=31142094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18962586U Pending JPS6392971U (en) | 1986-12-08 | 1986-12-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392971U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02281818A (en) * | 1989-04-24 | 1990-11-19 | Nippon Telegr & Teleph Corp <Ntt> | Serial-parallel converter |
-
1986
- 1986-12-08 JP JP18962586U patent/JPS6392971U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02281818A (en) * | 1989-04-24 | 1990-11-19 | Nippon Telegr & Teleph Corp <Ntt> | Serial-parallel converter |
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