JPS6262362U - - Google Patents
Info
- Publication number
- JPS6262362U JPS6262362U JP15071685U JP15071685U JPS6262362U JP S6262362 U JPS6262362 U JP S6262362U JP 15071685 U JP15071685 U JP 15071685U JP 15071685 U JP15071685 U JP 15071685U JP S6262362 U JPS6262362 U JP S6262362U
- Authority
- JP
- Japan
- Prior art keywords
- input
- buffer
- output
- data
- bit data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
Description
第１図はシリアル入出力インターフエースの設
置位置の関係を示す概略図、第２図は本考案のシ
リアル入出力インターフエースの概略構成を示す
ブロツク図である。
２……シリアル入出力インターフエース、６…
…入力バツフア、７……出力バツフア、８……入
力メモリバツフア、９……出力メモリバツフア、
１０……アイ・オーポート。
FIG. 1 is a schematic diagram showing the relationship between the installation positions of the serial input/output interface, and FIG. 2 is a block diagram showing the schematic configuration of the serial input/output interface of the present invention. 2...Serial input/output interface, 6...
...Input buffer, 7...Output buffer, 8...Input memory buffer, 9...Output memory buffer,
10...I Oport.
Claims (1)
データに変換する入力バツフアと、パラレルビツ
トデータをシリアルビツトデータに変換する出力
バツフアと、 上記入力バツフアからのデータを記憶し、その
記憶内容を適宜にアイ・オーポートの出力段へ渡
す入力メモリバツフアと、 上記アイ・オーポートの入力段からのデータを
受け取つて記憶し、その内容を適宜に出力バツフ
アへ渡す出力メモリバツフアと、 から成ることを特徴とするシリアル入出力インタ
ーフエース。 ２ 上記入力バツフアと出力バツフアとがシフト
レジスタで構成されている実用新案登録請求の範
囲第１項記載のシリアル入出力インターフエース
。[Claims for Utility Model Registration] 1. An input buffer for converting serial bit data input into parallel bit data, an output buffer for converting parallel bit data into serial bit data, and storing data from the input buffer and storing the data. It is characterized by consisting of an input memory buffer that appropriately passes the contents to the output stage of the I-O port, and an output memory buffer that receives and stores the data from the input stage of the I-O port, and passes the contents to the output buffer as appropriate. Serial input/output interface. 2. The serial input/output interface according to claim 1, wherein the input buffer and the output buffer are constituted by shift registers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15071685U JPS6262362U (en) | 1985-10-01 | 1985-10-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15071685U JPS6262362U (en) | 1985-10-01 | 1985-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6262362U true JPS6262362U (en) | 1987-04-17 |
Family
ID=31067109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15071685U Pending JPS6262362U (en) | 1985-10-01 | 1985-10-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6262362U (en) |
-
1985
- 1985-10-01 JP JP15071685U patent/JPS6262362U/ja active Pending
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