JPS61107049U - - Google Patents
Info
- Publication number
- JPS61107049U JPS61107049U JP19035884U JP19035884U JPS61107049U JP S61107049 U JPS61107049 U JP S61107049U JP 19035884 U JP19035884 U JP 19035884U JP 19035884 U JP19035884 U JP 19035884U JP S61107049 U JPS61107049 U JP S61107049U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- space
- processing circuit
- memory space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例の入力／出力空間切
換え回路１の構成を示すブロツク図、第２図は第
１図の実施例の入力／出力空間切換え回路１の回
路図、第３図は入力／出力空間切換え回路１の作
動状態を説明するための図である。
１…入力／出力空間切換え回路、２…中央演算
処理回路、４…アドレス変換回路、５…信号切換
え回路、７…ラツチ回路、１１…入力／出力空間
、１２…外部機器、１３…メモリ空間。
FIG. 1 is a block diagram showing the configuration of an input/output space switching circuit 1 according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the input/output space switching circuit 1 according to the embodiment of FIG. 1, and FIG. 1 is a diagram for explaining the operating state of the input/output space switching circuit 1. FIG. DESCRIPTION OF SYMBOLS 1... Input/output space switching circuit, 2... Central processing circuit, 4... Address conversion circuit, 5... Signal switching circuit, 7... Latch circuit, 11... Input/output space, 12... External device, 13... Memory space.
Claims (1)
空間と、 前記処理回路と外部機器との間に介在され、情
報のストア機能を有する入力／出力空間とを含み
、 入力／出力空間の情報の一部をメモリ空間内に
転送し、その転送されたメモリ空間の領域に予め
ストアされていた情報を、入力／出力空間の前記
転送した領域に転送することを特徴とする入力／
出力空間切換え回路。[Claims for Utility Model Registration] A processing circuit, a memory space that operates in close association with the processing circuit, and an input/output that is interposed between the processing circuit and an external device and has an information storage function. transfer a part of the information of the input/output space into the memory space, and transfer the information previously stored in the transferred area of the memory space to the transferred area of the input/output space; An input characterized by
Output space switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19035884U JPS61107049U (en) | 1984-12-15 | 1984-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19035884U JPS61107049U (en) | 1984-12-15 | 1984-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107049U true JPS61107049U (en) | 1986-07-07 |
Family
ID=30747810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19035884U Pending JPS61107049U (en) | 1984-12-15 | 1984-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107049U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745659A (en) * | 1980-09-03 | 1982-03-15 | Hitachi Ltd | Memory address managing device |
-
1984
- 1984-12-15 JP JP19035884U patent/JPS61107049U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745659A (en) * | 1980-09-03 | 1982-03-15 | Hitachi Ltd | Memory address managing device |
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