JPS61149197U - - Google Patents

Info

Publication number
JPS61149197U
JPS61149197U JP3129485U JP3129485U JPS61149197U JP S61149197 U JPS61149197 U JP S61149197U JP 3129485 U JP3129485 U JP 3129485U JP 3129485 U JP3129485 U JP 3129485U JP S61149197 U JPS61149197 U JP S61149197U
Authority
JP
Japan
Prior art keywords
input
data
controlling
transfer gate
gate according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3129485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3129485U priority Critical patent/JPS61149197U/ja
Publication of JPS61149197U publication Critical patent/JPS61149197U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路構成図で
ある。 11……データ入力端子、12a〜12h……
トランスフアゲート、13a〜13d……RAM
、14……データ出力端子、15……アドレス制
御回路、16……アドレスカウンタ、19……デ
コーダ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 11...Data input terminal, 12a to 12h...
Transfer gate, 13a-13d...RAM
, 14...Data output terminal, 15...Address control circuit, 16...Address counter, 19...Decoder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同一のアドレス空間を有する複数のRAMと、
これらの各RAMのデータ入力側及びデータ出力
側にそれぞれ設けられたトランスフアゲートと、
入力モードに応じて上記入力側トランスフアゲー
トを制御し、上記RAMへの入力を同時入力ある
いは指定アドレスに応じた選択入力に切換える手
段と、上記入力モードに応じて上記読出し/書込
み信号を上記各RAMに同時あるいは指定アドレ
スに応じて選択的に与える手段と、アドレスデー
タに応じて上記出力側トランスフアゲートを制御
し、上記RAMを選択して記憶データの読出しを
行なう手段とを具備したことを特徴とするデータ
記憶装置。
a plurality of RAMs having the same address space;
Transfer gates provided on the data input side and data output side of each of these RAMs,
means for controlling the input-side transfer gate according to the input mode and switching the inputs to the RAM to simultaneous input or selective input according to a designated address; and means for controlling the input side transfer gate according to the input mode; and means for controlling the output-side transfer gate according to address data to select the RAM and read the stored data. data storage device.
JP3129485U 1985-03-05 1985-03-05 Pending JPS61149197U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3129485U JPS61149197U (en) 1985-03-05 1985-03-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3129485U JPS61149197U (en) 1985-03-05 1985-03-05

Publications (1)

Publication Number Publication Date
JPS61149197U true JPS61149197U (en) 1986-09-13

Family

ID=30531771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3129485U Pending JPS61149197U (en) 1985-03-05 1985-03-05

Country Status (1)

Country Link
JP (1) JPS61149197U (en)

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