JPS6421452U - - Google Patents
Info
- Publication number
- JPS6421452U JPS6421452U JP11601287U JP11601287U JPS6421452U JP S6421452 U JPS6421452 U JP S6421452U JP 11601287 U JP11601287 U JP 11601287U JP 11601287 U JP11601287 U JP 11601287U JP S6421452 U JPS6421452 U JP S6421452U
- Authority
- JP
- Japan
- Prior art keywords
- data
- required minimum
- minimum weight
- data memory
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案の一実施例によるデータ分類
記憶装置のブロツク図、第２図及び第４図は第１
図に従つたデータメモリ内のデータ構成の具体的
な一例を示すデータメモリ構成図、第３図は各種
出力データの具体的な一実施例を示すデータ出力
フオーマツト、第５図は従来のデータ分類記憶装
置のブロツク図、第６図は第５図に従つたデータ
メモリ内のデータ構成の具体的な一例を示すデー
タメモリ構成図である。
図において、１はデータ出力装置、２は各種出
力データ、３はデータメモリ、４はアドレス作成
回路、５はアドレス制御信号を示す。なお、図中
、同一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram of a data classification storage device according to an embodiment of this invention, and FIGS.
A data memory configuration diagram showing a specific example of the data structure in the data memory according to the figure, FIG. 3 is a data output format showing a specific example of various output data, and FIG. 5 is a conventional data classification. FIG. 6 is a block diagram of the storage device, which is a data memory configuration diagram showing a specific example of the data configuration in the data memory according to FIG. In the figure, 1 is a data output device, 2 is various output data, 3 is a data memory, 4 is an address generation circuit, and 5 is an address control signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
るデータに着目し、そのデータの必要とする最小
重み範囲毎に順次並べた構成のデータメモリと、
このデータメモリのアドレス制御信号として、前
記着目データの必要最小重み以上を直接接続して
使用したことを特徴とするデータ分類記憶装置。 A data memory configured to focus on certain data among various output data from a data output device and sequentially arrange the data according to the required minimum weight range;
A data classification storage device characterized in that a signal equal to or higher than the required minimum weight of the data of interest is directly connected and used as an address control signal of the data memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11601287U JPS6421452U (en) | 1987-07-28 | 1987-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11601287U JPS6421452U (en) | 1987-07-28 | 1987-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6421452U true JPS6421452U (en) | 1989-02-02 |
Family
ID=31358181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11601287U Pending JPS6421452U (en) | 1987-07-28 | 1987-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6421452U (en) |
-
1987
- 1987-07-28 JP JP11601287U patent/JPS6421452U/ja active Pending