JPS61168444U - - Google Patents
Info
- Publication number
- JPS61168444U JPS61168444U JP5224985U JP5224985U JPS61168444U JP S61168444 U JPS61168444 U JP S61168444U JP 5224985 U JP5224985 U JP 5224985U JP 5224985 U JP5224985 U JP 5224985U JP S61168444 U JPS61168444 U JP S61168444U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- read
- address
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例による記憶装置を
示すブロツク図、第２図は従来の記憶装置を示す
ブロツク図である。
１はメモリ、２はアドレス・パス、３はデータ
パ・パス、４は制御回路、５は転送路、６はアド
レス／データ判定回路。なお、各図中、同一符号
は同一または相当部分を示す。
FIG. 1 is a block diagram showing a storage device according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional storage device. 1 is a memory, 2 is an address path, 3 is a data path, 4 is a control circuit, 5 is a transfer path, and 6 is an address/data determination circuit. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
レス信号を与えるアドレス・パスと、上記アドレ
ス信号に基づいてメモリより読み出されたデータ
が転送されるデータ・パスと、上記メモリから読
み出されたデータがアドレスか目的のデータかを
判定するアドレス／データ判定回路と、この判定
回路の判定結果、上記メモリから読み出されたデ
ータがアドレスであるときに、そのデータを、上
記メモリより目的のデータを読み出すためのアド
レス信号として上記メモリのアドレス・パスに伝
える転送路とを備え、この読み出されたアドレス
信号を上記転送路を経由して上記メモリに送出し
て目的のデータを読み出すことを特徴とする記憶
装置。 A memory that stores data, an address path that provides an address signal to this memory, a data path that transfers data read from the memory based on the address signal, and a data path that transfers the data read from the memory. An address/data determination circuit that determines whether the data is an address or the target data; and when the determination result of this determination circuit is that the data read from the memory is an address, the data is read from the memory, and the target data is read from the memory. and a transfer path for transmitting an address signal to the address path of the memory, and the read address signal is sent to the memory via the transfer path to read the target data. Storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224985U JPS61168444U (en) | 1985-04-09 | 1985-04-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224985U JPS61168444U (en) | 1985-04-09 | 1985-04-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168444U true JPS61168444U (en) | 1986-10-18 |
Family
ID=30572033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5224985U Pending JPS61168444U (en) | 1985-04-09 | 1985-04-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168444U (en) |
-
1985
- 1985-04-09 JP JP5224985U patent/JPS61168444U/ja active Pending
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