JPS5816955U - PCM signal generator - Google Patents

PCM signal generator

Info

Publication number
JPS5816955U
JPS5816955U JP10814681U JP10814681U JPS5816955U JP S5816955 U JPS5816955 U JP S5816955U JP 10814681 U JP10814681 U JP 10814681U JP 10814681 U JP10814681 U JP 10814681U JP S5816955 U JPS5816955 U JP S5816955U
Authority
JP
Japan
Prior art keywords
control information
pcm signal
signal generator
storage section
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10814681U
Other languages
Japanese (ja)
Other versions
JPH018043Y2 (en
Inventor
正信 酒井
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP10814681U priority Critical patent/JPS5816955U/en
Publication of JPS5816955U publication Critical patent/JPS5816955U/en
Application granted granted Critical
Publication of JPH018043Y2 publication Critical patent/JPH018043Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面はこの考案に係わるＰＣＭ信号発生装置の一実施例
を示す構成図である。 １２・・・演算処理器、１３・・・タイミング回路、１
４・−ＰＣＭ送出タイミング制御器、１５．１６・・・
第１、第２の記憶部。The drawing is a block diagram showing an embodiment of a PCM signal generator according to the invention. 12... Arithmetic processor, 13... Timing circuit, 1
4.-PCM sending timing controller, 15.16...
first and second storage units;

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 共通の制御情報が記憶された第１の記憶部と、固有の制
御情報が記憶された第２の記憶部と、この固有の制御情
報に応じたタイミング信号を発生するタイミング回路と
、前記第１、第２の記憶部よりそれぞれ制御情報が供給
されるとともに前記タイミング信号が供給され前記制御
情報で規定される所定形式のＰＣＭ信号を生成する演算
処理器と、このＰＣＭ信号および前記タイミング信号が
供給された所定のビットレイトのＰＣＭ信号を送出する
タイミング制御器とを具備したことを特徴とするＰＣＭ
信号発生装置。a first storage section in which common control information is stored; a second storage section in which unique control information is stored; a timing circuit that generates a timing signal according to the unique control information; , an arithmetic processor that is supplied with control information and the timing signal from a second storage section and generates a PCM signal in a predetermined format defined by the control information; and a timing controller for transmitting a PCM signal at a predetermined bit rate.
Signal generator.
JP10814681U 1981-07-21 1981-07-21 PCM signal generator Granted JPS5816955U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10814681U JPS5816955U (en) 1981-07-21 1981-07-21 PCM signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10814681U JPS5816955U (en) 1981-07-21 1981-07-21 PCM signal generator

Publications (2)

Publication Number Publication Date
JPS5816955U true JPS5816955U (en) 1983-02-02
JPH018043Y2 JPH018043Y2 (en) 1989-03-02

Family

ID=29902560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10814681U Granted JPS5816955U (en) 1981-07-21 1981-07-21 PCM signal generator

Country Status (1)

Country Link
JP (1) JPS5816955U (en)

Also Published As

Publication number Publication date
JPH018043Y2 (en) 1989-03-02

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