JPS6356451U - - Google Patents
Info
- Publication number
- JPS6356451U JPS6356451U JP14776286U JP14776286U JPS6356451U JP S6356451 U JPS6356451 U JP S6356451U JP 14776286 U JP14776286 U JP 14776286U JP 14776286 U JP14776286 U JP 14776286U JP S6356451 U JPS6356451 U JP S6356451U
- Authority
- JP
- Japan
- Prior art keywords
- computer
- external image
- image memory
- read
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Image Input (AREA)
Description
図は本考案のメモリ制御装置の一実施例を示し
たブロツク図である。
１……入出力制御回路、２，５……選択回路、
３……主制御回路、４……計数回路、６……外部
画像メモリ、１３……計算機、１４……出力端末
装置。
The figure is a block diagram showing one embodiment of the memory control device of the present invention. 1... Input/output control circuit, 2, 5... Selection circuit,
3... Main control circuit, 4... Counting circuit, 6... External image memory, 13... Computer, 14... Output terminal device.
Claims (1)
るメモリ制御装置において、前記計算機から与え
られた任意のアドレスを初期値としてこのアドレ
スを外部画像メモリに出力するアドレス出力手段
と、前記計算機から出力される書き込み、読み出
し制御信号に同期して前記アドレス出力手段が出
力するアドレスを更新する制御を行い、且つ、前
記書き込み、読み出し制御信号に同期して前記外
部画像メモリに対して画像データの読み書き制御
を行う制御手段と、前記計算機と前記外部画像メ
モリ間の画像データの伝送を行うバス経路を形成
するバス切換手段と、前記外部画像メモリから読
み出した画像データを出力端末装置に出力する時
には出力端末装置の画像データ要求に従つて前記
アドレス出力手段が出力するアドレスを更新する
制御を行い、且つ、前記外部画像メモリから画像
データを読み出す制御を行うデータ読み出し制御
手段とを具備したことを特徴とするメモリ制御装
置。 In a memory control device that serves as an interface between an external image memory and a computer, address output means outputs an arbitrary address given from the computer as an initial value to the external image memory, and a write output from the computer; A control means that performs control to update the address output by the address output means in synchronization with a read control signal, and performs control to read and write image data from and to the external image memory in synchronization with the write and read control signals. a bus switching means for forming a bus route for transmitting image data between the computer and the external image memory; and a bus switching means for forming a bus route for transmitting image data between the computer and the external image memory; A memory control device comprising: data read control means that performs control to update the address output by the address output means in accordance with a request, and performs control to read image data from the external image memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14776286U JPS6356451U (en) | 1986-09-29 | 1986-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14776286U JPS6356451U (en) | 1986-09-29 | 1986-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356451U true JPS6356451U (en) | 1988-04-15 |
Family
ID=31061424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14776286U Pending JPS6356451U (en) | 1986-09-29 | 1986-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356451U (en) |
-
1986
- 1986-09-29 JP JP14776286U patent/JPS6356451U/ja active Pending
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