JPS6173192U - - Google Patents
Info
- Publication number
- JPS6173192U JPS6173192U JP15780584U JP15780584U JPS6173192U JP S6173192 U JPS6173192 U JP S6173192U JP 15780584 U JP15780584 U JP 15780584U JP 15780584 U JP15780584 U JP 15780584U JP S6173192 U JPS6173192 U JP S6173192U
- Authority
- JP
- Japan
- Prior art keywords
- image
- image memory
- main control
- control circuit
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 1
Description
第１図は本考案の画像表示装置の一実施例を示
すブロツク図、第２図は本考案の他の実施例を示
すブロツク図、第３図は従来の画像表示装置のブ
ロツク図である。
１０…ＣＰＵ（主制御回路）、１３…第１画像
メモリ、１４…第２画像メモリ、１６…単方向性
バスバツフア、１６′…双方向性バスバツフア、
Ｂ５，Ｂ６…データバス、Ｂ３…ＣＰＵデータバ
ス。
FIG. 1 is a block diagram showing one embodiment of the image display device of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional image display device. 10... CPU (main control circuit), 13... first image memory, 14... second image memory, 16... unidirectional bus buffer, 16'... bidirectional bus buffer,
B5 , B6 ...data bus, B3 ...CPU data bus.
Claims (1)
が書込みまたは読出される第１画像メモリと、該
第１画像メモリと等価な構成の第２画像メモリと
、前記第１、第２画像メモリ間に設けられた第１
データバスと、該第１データバスに設けられたバ
スバツフアと、前記主制御回路と前記第１データ
バス間に設けられた第２データバスとを備え、前
記第１画像メモリが前記主制御回路によつて書込
みまたは読出されないとき前記バスバツフアが導
通状態になり、前記第１画像メモリの画像情報が
読出されて画面上に表示されると同時にこの画像
情報が前記第２画像メモリに書込まれ、前記第１
画像メモリが前記主制御回路により前記第２デー
タバスを介して書込みまたは読出されるとき前記
バスバツフアが非導通状態になり、前記第２画像
メモリに書込まれた第１画像メモリの画像情報を
画面上に表示するように制御されるように構成し
てなる画像表示装置。 a main control circuit; a first image memory into which image information is written or read by the main control circuit; a second image memory having an equivalent configuration to the first image memory; and the first and second image memories. The first
a data bus, a bus buffer provided on the first data bus, and a second data bus provided between the main control circuit and the first data bus, wherein the first image memory is connected to the main control circuit. Therefore, when writing or reading is not performed, the bus buffer becomes conductive, and at the same time as the image information in the first image memory is read out and displayed on the screen, this image information is written into the second image memory, and the image information in the first image memory is read out and displayed on the screen. 1st
When the image memory is written or read by the main control circuit via the second data bus, the bus buffer becomes non-conductive, and the image information of the first image memory written to the second image memory is transferred to the screen. An image display device configured to be controlled to display an image on an image.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15780584U JPS6173192U (en) | 1984-10-18 | 1984-10-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15780584U JPS6173192U (en) | 1984-10-18 | 1984-10-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6173192U true JPS6173192U (en) | 1986-05-17 |
Family
ID=30715793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15780584U Pending JPS6173192U (en) | 1984-10-18 | 1984-10-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6173192U (en) |
-
1984
- 1984-10-18 JP JP15780584U patent/JPS6173192U/ja active Pending
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