JPS6457533U - - Google Patents
Info
- Publication number
- JPS6457533U JPS6457533U JP15027087U JP15027087U JPS6457533U JP S6457533 U JPS6457533 U JP S6457533U JP 15027087 U JP15027087 U JP 15027087U JP 15027087 U JP15027087 U JP 15027087U JP S6457533 U JPS6457533 U JP S6457533U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- parity
- data
- extended
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Description
第１図は本考案の一実施例のコンピユータシス
テムにおけるパリテイチエツク機構の構成を説明
するためのブロツク図、第２図は従来のコンピユ
ータシステムにおけるパリテイチエツク機構の構
成を説明するためのブロツク図である。
１１…メインメモリ、１２…拡張メモリ、１３
…パリテイメモリ、１４…パリテイチエツク回路
、１５…コネクタ。
FIG. 1 is a block diagram for explaining the configuration of a parity check mechanism in a computer system according to an embodiment of the present invention, and FIG. 2 is a block diagram for explaining the configuration of a parity check mechanism in a conventional computer system. It is. 11...Main memory, 12...Extended memory, 13
... Parity memory, 14... Parity check circuit, 15... Connector.
Claims (1)
のデータの書込みおよび読出しを行うことにより
所定の情報処理の実行が可能とされたコンピユー
タシステムにおいて、前記拡張メモリおよびシス
テム本体のメインメモリに書込まれたデータのパ
リテイデータを格納可能なパリテイメモリと、前
記拡張メモリおよびメインメモリに書込まれたデ
ータから前記パリテイメモリに格納すべきパリテ
イデータを抽出しかつ前記拡張メモリおよびメイ
ンメモリからのデータの読出しに応じて前記パリ
テイメモリに格納されたパリテイデータを用いて
読出されたデータのパリテイチエツクを行うパリ
テイチエツク回路とを具備したことを特徴とする
コンピユータシステム。 In a computer system in which a predetermined information process can be executed by installing an extended memory and writing and reading data to and from the extended memory, information written to the extended memory and the main memory of the system main body is used. a parity memory capable of storing parity data of data written to the extended memory; and a parity memory capable of storing parity data of the data written in the expanded memory and the main memory, and extracting parity data to be stored in the parity memory from the data written in the expanded memory and the main memory, and extracting the parity data to be stored in the parity memory from the expanded memory and the main memory. 1. A computer system comprising: a parity check circuit that performs a parity check on read data using parity data stored in the parity memory in response to read data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15027087U JPS6457533U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15027087U JPS6457533U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457533U true JPS6457533U (en) | 1989-04-10 |
Family
ID=31423264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15027087U Pending JPS6457533U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457533U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52120633A (en) * | 1976-04-02 | 1977-10-11 | Hitachi Ltd | Error correction logic system |
-
1987
- 1987-09-30 JP JP15027087U patent/JPS6457533U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52120633A (en) * | 1976-04-02 | 1977-10-11 | Hitachi Ltd | Error correction logic system |
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