JPS61180341U - - Google Patents
Info
- Publication number
- JPS61180341U JPS61180341U JP6444585U JP6444585U JPS61180341U JP S61180341 U JPS61180341 U JP S61180341U JP 6444585 U JP6444585 U JP 6444585U JP 6444585 U JP6444585 U JP 6444585U JP S61180341 U JPS61180341 U JP S61180341U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- parity check
- signal
- input
- performs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案に係る装置の一実施例の構成ブ
ロツク図、第２図及び第３図はその動作波形図で
ある。
１…判定回路、２…パリテイチエツク回路、３
…応答信号返信回路、４…メモリアクセス回路、
５…メモリ素子。
FIG. 1 is a block diagram of an embodiment of the apparatus according to the present invention, and FIGS. 2 and 3 are operational waveform diagrams thereof. 1... Judgment circuit, 2... Parity check circuit, 3
...Response signal return circuit, 4...Memory access circuit,
5...Memory element.
Claims (1)
力しこのアドレス信号によつて自分が選択された
かどうか判定する判定回路と、この判定回路から
の判定結果を示す信号とライトデータとを入力し
ライトデータのパリテイチエツクを行なうパリテ
イチエツク回路と、このパリテイチエツク回路の
チエツク結果が入力され正常である時応答信号を
ホスト側に返信する応答信号返信回路と、リード
命令とライト命令とによつてメモリ素子にメモリ
アクセスを行なうメモリアクセス回路とを備えた
メモリ装置。 A determination circuit receives a selection signal and an address signal from the master side and determines whether or not it has been selected based on this address signal, and a signal indicating the determination result from this determination circuit and write data are input. a parity check circuit that performs a parity check; a response signal return circuit that returns a response signal to the host side when the check result of the parity check circuit is input and normal; and a read command and a write command. A memory device comprising a memory access circuit that performs memory access to a memory element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6444585U JPS61180341U (en) | 1985-04-30 | 1985-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6444585U JPS61180341U (en) | 1985-04-30 | 1985-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61180341U true JPS61180341U (en) | 1986-11-11 |
Family
ID=30595537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6444585U Pending JPS61180341U (en) | 1985-04-30 | 1985-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61180341U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153592A (en) * | 1980-04-25 | 1981-11-27 | Mitsubishi Electric Corp | Output memory device |
-
1985
- 1985-04-30 JP JP6444585U patent/JPS61180341U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153592A (en) * | 1980-04-25 | 1981-11-27 | Mitsubishi Electric Corp | Output memory device |
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