JPH02116346U - - Google Patents
Info
- Publication number
- JPH02116346U JPH02116346U JP2514789U JP2514789U JPH02116346U JP H02116346 U JPH02116346 U JP H02116346U JP 2514789 U JP2514789 U JP 2514789U JP 2514789 U JP2514789 U JP 2514789U JP H02116346 U JPH02116346 U JP H02116346U
- Authority
- JP
- Japan
- Prior art keywords
- data
- dual port
- parallel
- serial
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims description 7
- 230000015654 memory Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案の一実施例に係わるバスインタ
ーフエイス回路の構成を示すブロツク図、第２図
は一般的なコンピユータ制御システムを示す図で
ある。
１０……入出力バス、１１……バスインターフ
エイス制御部、１２……アドレスデコーダ、１３
ａ……データ出力用デユアルポートメモリ、１３
ｂ……データ入力用デユアルポートメモリ、１４
ａ，１４ｂ……コントローラ、１５……パラレル
／シリアル変換部、１６……シリアル／パラレル
変換部。
FIG. 1 is a block diagram showing the configuration of a bus interface circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a general computer control system. 10...I/O bus, 11...Bus interface control unit, 12...Address decoder, 13
a...Dual port memory for data output, 13
b...Dual port memory for data input, 14
a, 14b...controller, 15...parallel/serial converter, 16...serial/parallel converter.
Claims (1)
れ入力データ及び出力データの書込まれるデータ
入力用のデユアルポートメモリ及びデータ出力用
のデユアルポートメモリと、この２つのデユアル
ポートメモリに対するデータの書込みと読出しと
を制御する手段と、上記データ出力用のデユアル
ポートメモリから読出されたパラレルデータをシ
リアルデータに変換し他のデータ処理装置に出力
するパラレル／シリアル変換器と、他のデータ処
理装置から入力されるシリアルデータをパラレル
データに変換し上記データ入力用のデユアルポー
トメモリに出力するシリアル／パラレル変換器と
を具備したことを特徴とするバスインターフエイ
ス回路。 A dual port memory for data input and a dual port memory for data output connected to the input/output bus of the data processing device and into which input data and output data are respectively written, and data writing and reading to and from the two dual port memories. a parallel/serial converter that converts the parallel data read from the dual port memory for data output into serial data and outputs it to another data processing device; A bus interface circuit comprising a serial/parallel converter that converts serial data into parallel data and outputs the data to the dual port memory for data input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2514789U JPH02116346U (en) | 1989-03-07 | 1989-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2514789U JPH02116346U (en) | 1989-03-07 | 1989-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02116346U true JPH02116346U (en) | 1990-09-18 |
Family
ID=31245626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2514789U Pending JPH02116346U (en) | 1989-03-07 | 1989-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02116346U (en) |
-
1989
- 1989-03-07 JP JP2514789U patent/JPH02116346U/ja active Pending
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