JPS6214541U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing another embodiment of the present invention;
FIG. 3 is a block diagram showing a conventional direct memory transfer device. Explanation of symbols: 3, 3a, 3b, 7...DMA controller, 4, 4a, 4b...P/S converter,
5, 5a, 5b...FIFO, 6, 6a, 6b...
...S/P converter, 8...Processor, 9...Logic operation unit, 10...Memory, 10a, 10b, 1
0c...Memory area.

Claims (1)

[Claims for Utility Model Registration] (1) DMA transfer of data from a first memory area in which data having arbitrary bit width at the beginning or end of a word group is stored to a second memory area A computer system that requires the following: a first DMA controller that reads data in units of words from a memory area in which the data before transfer is stored; a FIFO that reads data given through the controller or processor in the order in which it is input; A second DMA controller is provided that transfers data output from the FIFO to the second memory area, and stores data of the arbitrary bit width in the FIFO via the processor, and also stores data in word units. stored in the FIFO via the first DMA controller, and stored in the second DMA controller.
A direct memory transfer device characterized by outputting to a controller. (2) A utility model registration request characterized in that a logic operation device is provided between the FIFO and the second DMA controller, and performs a logic operation on the output data of the FIFO and data read from another memory area. The direct memory transfer device according to item 1.