JPS63155552U - - Google Patents
Info
- Publication number
- JPS63155552U JPS63155552U JP7243187U JP7243187U JPS63155552U JP S63155552 U JPS63155552 U JP S63155552U JP 7243187 U JP7243187 U JP 7243187U JP 7243187 U JP7243187 U JP 7243187U JP S63155552 U JPS63155552 U JP S63155552U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- data
- output
- fifo buffer
- counter means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本考案のデータ転送バツフア回路の第
１の実施例を示すブロツク図、第２図は本考案の
第２の実施例を示すブロツク図、第３図は第２図
の動作を説明するタイミング図、第４図は本考案
の第３の実施例を示すブロツク図、第５図は第４
図の動作を説明するタイミング図、第６図は従来
のデータ転送バツフア回路を示すブロツク図、第
７図は第６図のＦＩＦＯバツフアにトランスペア
レント形式で格納されるデータの内容を示す説明
図である。
１１，１４，３１，３３……ＣＰＵ、１２，３
２……データ用ＦＩＦＯバツフア、１６，２０…
…カウンタ、１７……ラツチ回路、１８……比較
器、２７，３４……データ長用ＦＩＦＯバツフア
。
Fig. 1 is a block diagram showing a first embodiment of the data transfer buffer circuit of the present invention, Fig. 2 is a block diagram showing a second embodiment of the invention, and Fig. 3 explains the operation of Fig. 2. 4 is a block diagram showing the third embodiment of the present invention, and FIG. 5 is a timing diagram showing the fourth embodiment of the present invention.
6 is a block diagram showing a conventional data transfer buffer circuit. FIG. 7 is an explanatory diagram showing the contents of data stored in the FIFO buffer in FIG. 6 in a transparent format. . 11, 14, 31, 33... CPU, 12, 3
2... FIFO buffer for data, 16, 20...
... Counter, 17 ... Latch circuit, 18 ... Comparator, 27, 34 ... FIFO buffer for data length.
Claims (1)
ータ転送を行なうデータ転送バツフア回路におい
て、 第１のマイクロプロセツサから出力されるデー
タを格納し第２のマイクロプロセツサに転送する
ＦＩＦＯバツフア回路と、 第１のマイクロプロセツサが前記ＦＩＦＯバツ
フア回路へ書き込んだデータの数をカウントする
第１のカウンタ手段と、 データの区切りで前記第１のカウンタ手段の出
力を保持する保持回路と、 第２のマイクロプロセツサが前記ＦＩＦＯバツ
フアから読み出したデータの数をカウントする第
２のカウンタ手段と、 前記保持回路の出力と前記第２のカウンタ手段
の出力とを比較して、両方の出力が等しいときに
第２のマイクロプロセツサに対して一致信号を出
力する比較回路とを具備したことを特徴とするデ
ータ転送バツフア回路。[Claims for Utility Model Registration] In a data transfer buffer circuit that transfers data between two microprocessors, a first and a second microprocessor, the data output from the first microprocessor is stored and the second microprocessor a FIFO buffer circuit for transferring data to the FIFO buffer circuit; a first counter means for counting the number of data written by a first microprocessor to the FIFO buffer circuit; and an output of the first counter means is held at data breaks. a second counter means for counting the number of data read out from the FIFO buffer by a second microprocessor; and comparing the output of the holding circuit and the output of the second counter means. , and a comparison circuit that outputs a match signal to a second microprocessor when both outputs are equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7243187U JPS63155552U (en) | 1986-11-19 | 1987-05-15 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17667586 | 1986-11-19 | ||
| JP7243187U JPS63155552U (en) | 1986-11-19 | 1987-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155552U true JPS63155552U (en) | 1988-10-12 |
Family
ID=33454971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7243187U Pending JPS63155552U (en) | 1986-11-19 | 1987-05-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155552U (en) |
-
1987
- 1987-05-15 JP JP7243187U patent/JPS63155552U/ja active Pending
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