JPS6085443U - codec circuit - Google Patents
codec circuitInfo
- Publication number
- JPS6085443U JPS6085443U JP17692483U JP17692483U JPS6085443U JP S6085443 U JPS6085443 U JP S6085443U JP 17692483 U JP17692483 U JP 17692483U JP 17692483 U JP17692483 U JP 17692483U JP S6085443 U JPS6085443 U JP S6085443U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- codec
- serial
- circuit
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Communication Control (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案のコーデック回路の一実施例を示した
ブロック図、第２図は第１図の動作を説明する図である
。
１・・・・・・シリアル／パラレル変換回路、２・・・
・・・同期信号発生回路、３・・・・・・クロック発生
回路、４・・・００．バッファ回路、５・・・・・・コ
ーデック。FIG. 1 is a block diagram showing an embodiment of the codec circuit of the present invention, and FIG. 2 is a diagram explaining the operation of FIG. 1. 1... Serial/parallel conversion circuit, 2...
. . . Synchronous signal generation circuit, 3 . . . Clock generation circuit, 4 . . . 00. Buffer circuit, 5... codec.
Claims (1)
グ信号からディジタルハイウェイ信号に変換するコーデ
ック回路において、ディジタルハイウェイ信号をシリア
ル信号からパラレル信号に、パラレル信号をシリアルの
ディジタルハイウェイ信号に変換するシリアル／パラレ
ル変換回路と、該ディジタルハイウェイ信号から一定周
期の同期信号を発生する同期信号発生回路と、コーデッ
クに必要なりロックと前記一定周期の同期信号からコー
デックに必要な同期信号とを発生するクロック発生回路
と、前記シリアル／パラレル変換回路からのパラレル信
号をコーデックに転送ｊる時にシリアル信号に変換して
転送し、又は、コーデックからのシリアル信号をシリア
ル／パラレル変換回路に転送する時にパラレル信号に変
換して転送するバッファ回路と、コーデックとを有する
ことを特徴とするコーデック回路。In a codec circuit that converts a digital highway signal to an analog signal and from an analog signal to a digital highway signal, a serial/parallel conversion circuit that converts the digital highway signal from a serial signal to a parallel signal and the parallel signal to a serial digital highway signal; a synchronization signal generation circuit that generates a synchronization signal of a constant period from the digital highway signal; a clock generation circuit that generates a lock necessary for the codec and a synchronization signal necessary for the codec from the synchronization signal of the constant period; A buffer circuit that converts a parallel signal from a parallel conversion circuit into a serial signal when transferring it to a codec, or converts it into a parallel signal when transferring a serial signal from a codec to a serial/parallel conversion circuit. A codec circuit comprising: and a codec.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17692483U JPS6085443U (en) | 1983-11-16 | 1983-11-16 | codec circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17692483U JPS6085443U (en) | 1983-11-16 | 1983-11-16 | codec circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6085443U true JPS6085443U (en) | 1985-06-12 |
Family
ID=30384519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17692483U Pending JPS6085443U (en) | 1983-11-16 | 1983-11-16 | codec circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085443U (en) |
-
1983
- 1983-11-16 JP JP17692483U patent/JPS6085443U/en active Pending
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