JPS6136886U - Synchronous signal discrimination circuit - Google Patents
Synchronous signal discrimination circuitInfo
- Publication number
- JPS6136886U JPS6136886U JP12126884U JP12126884U JPS6136886U JP S6136886 U JPS6136886 U JP S6136886U JP 12126884 U JP12126884 U JP 12126884U JP 12126884 U JP12126884 U JP 12126884U JP S6136886 U JPS6136886 U JP S6136886U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- circuit
- exclusive
- gate
- discrimination circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係る同期信号判別回路の実施例を示す
回路図、第２図および第３図は第１論理回路および第２
論理回路の動作を示し、第２図は入力同期信号が正極性
の場合のタイミングチャート、第３図は同信号が負極性
の場合のタイミングチャート、第４図は前記同期信号判
別回路の全体にわたる動作を説明するタイミングチャー
トである。
２ａ・・・第１のエクスクルーシブオアゲート、２ｂ・
・・第２のエクスクールシブオアゲート、２ｃ・・・第
３のエクスクルーシブオアゲート、５ａ・・・第１論理
回路、５ｂ・・・第２論理回路、７ａ・・・積分回路、
７ｂ・・・積分回路。FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal discriminating circuit according to the present invention, and FIGS. 2 and 3 show a first logic circuit and a second logic circuit.
The operation of the logic circuit is shown, and FIG. 2 is a timing chart when the input synchronization signal has positive polarity, FIG. 3 is a timing chart when the same signal is negative polarity, and FIG. 4 shows the entire synchronization signal discrimination circuit. It is a timing chart explaining operation. 2a...first exclusive or gate, 2b...
...Second exclusive OR gate, 2c...Third exclusive OR gate, 5a...First logic circuit, 5b...Second logic circuit, 7a...Integrator circuit,
7b...integrator circuit.
Claims (3)
第１のエクスルーシブオアゲートに入力されて正極性の
同期信号を出力する第１論理回路と、 第２の同期信号と積分回路を経た該同期信号とが第２の
エクスクールシブオアゲートに入力，されて正極性の同
期信号を出力する第２論理回路とが並列に接続され、そ
れら２つの論理回路の出力が第３のエクスクルーシブオ
アゲートに入力されてなることを特徴とする同期信号判
別回路。(1) A first logic circuit that outputs a positive polarity synchronization signal by inputting the first synchronization signal and the synchronization signal that has passed through the integrating circuit into a first exclusive OR gate, and integrating the second synchronization signal. The synchronization signal that has passed through the circuit is input to a second exclusive OR gate, and a second logic circuit that outputs a positive polarity synchronization signal is connected in parallel, and the outputs of these two logic circuits are connected to a third exclusive OR gate. A synchronous signal discrimination circuit characterized in that it is input to an exclusive OR gate.
号が垂直同期信号である実用新案登録請求の範囲第１項
記載の同期信号判別回路。(2) The synchronization signal discriminating circuit according to claim 1, wherein the first synchronization signal is a horizontal synchronization signal and the second synchronization signal is a vertical synchronization signal.
号が無信号である実用新案登録請求の範囲第１項記載の
同期信号判別回路。(3) The synchronization signal discriminating circuit according to claim 1, wherein the first synchronization signal is a composite synchronization signal and the second synchronization signal is no signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12126884U JPS6136886U (en) | 1984-08-07 | 1984-08-07 | Synchronous signal discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12126884U JPS6136886U (en) | 1984-08-07 | 1984-08-07 | Synchronous signal discrimination circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6136886U true JPS6136886U (en) | 1986-03-07 |
| JPH0238314Y2 JPH0238314Y2 (en) | 1990-10-16 |
Family
ID=30680056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12126884U Granted JPS6136886U (en) | 1984-08-07 | 1984-08-07 | Synchronous signal discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136886U (en) |
-
1984
- 1984-08-07 JP JP12126884U patent/JPS6136886U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0238314Y2 (en) | 1990-10-16 |
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