JPS587217U - Master clock generation circuit - Google Patents
Master clock generation circuitInfo
- Publication number
- JPS587217U JPS587217U JP9900381U JP9900381U JPS587217U JP S587217 U JPS587217 U JP S587217U JP 9900381 U JP9900381 U JP 9900381U JP 9900381 U JP9900381 U JP 9900381U JP S587217 U JPS587217 U JP S587217U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock generation
- generation circuit
- master clock
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例を示す回路ブロック図である。
主な図番の説明、２・・・ＰＬＬ回路、３・・・信号欠
落検出回路、６・・・発振回路、７・・・クロック切換
回路。The figure is a circuit block diagram showing one embodiment of the present invention. Explanation of main figure numbers, 2...PLL circuit, 3...signal loss detection circuit, 6...oscillation circuit, 7...clock switching circuit.
Claims (1)
路と発掘周波数を−にして安定に発振する発振回路と、
再生垂直同期信号の欠落を検出する信号欠落検出回路と
、該検出出力により前記ＰＬＬ回路の出力に代えて前記
発振回路の出力を選択導出するクロック切換回路とをそ
れぞれ配することを特徴とするマスタークロック発生回
路。a PLL circuit that synchronizes with a reproduced vertical synchronization signal; an oscillation circuit that stably oscillates with the excavation frequency set to - from the PLL circuit;
A master comprising: a signal loss detection circuit for detecting loss of a reproduced vertical synchronization signal; and a clock switching circuit for selectively deriving the output of the oscillation circuit in place of the output of the PLL circuit based on the detection output. Clock generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9900381U JPS587217U (en) | 1981-07-02 | 1981-07-02 | Master clock generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9900381U JPS587217U (en) | 1981-07-02 | 1981-07-02 | Master clock generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS587217U true JPS587217U (en) | 1983-01-18 |
Family
ID=29893750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9900381U Pending JPS587217U (en) | 1981-07-02 | 1981-07-02 | Master clock generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS587217U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05199107A (en) * | 1992-01-17 | 1993-08-06 | Hitachi Ltd | Phase control system for system clock |
-
1981
- 1981-07-02 JP JP9900381U patent/JPS587217U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05199107A (en) * | 1992-01-17 | 1993-08-06 | Hitachi Ltd | Phase control system for system clock |
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