JPS6140761U - PLL circuit - Google Patents

PLL circuit

Info

Publication number
JPS6140761U
JPS6140761U JP12477484U JP12477484U JPS6140761U JP S6140761 U JPS6140761 U JP S6140761U JP 12477484 U JP12477484 U JP 12477484U JP 12477484 U JP12477484 U JP 12477484U JP S6140761 U JPS6140761 U JP S6140761U
Authority
JP
Japan
Prior art keywords
pll circuit
digital data
reproduced digital
frequency
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12477484U
Other languages
Japanese (ja)
Inventor
弘行 林
裕 宮部
啓文 村瀬
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP12477484U priority Critical patent/JPS6140761U/en
Publication of JPS6140761U publication Critical patent/JPS6140761U/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１区は本考案の実施例を示す構成図、第２図はその説
明のための図、第３図は静止画記録再生装置の一例を示
す構成図、第４図〜第１４図は夫々その説明のための図
である。 １７はイコライザ、２３はＰＬＬ回路、５６は切換スイ
ッチである。Section 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the same, FIG. 3 is a block diagram showing an example of a still image recording and reproducing device, and FIGS. 4 to 14 are respectively It is a figure for the explanation. 17 is an equalizer, 23 is a PLL circuit, and 56 is a changeover switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 再生デジタルデータとこの再生デジタルデータ周波数に
略等しい周波数の発振出力とが基準信号．とじて切換供
給され、再生クロツク信号が得られるＰＬＬ回路。The reproduced digital data and the oscillation output with a frequency approximately equal to the frequency of the reproduced digital data are the reference signal. A PLL circuit that is switched and supplied to obtain a regenerated clock signal.
JP12477484U 1984-08-16 1984-08-16 PLL circuit Pending JPS6140761U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12477484U JPS6140761U (en) 1984-08-16 1984-08-16 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12477484U JPS6140761U (en) 1984-08-16 1984-08-16 PLL circuit

Publications (1)

Publication Number Publication Date
JPS6140761U true JPS6140761U (en) 1986-03-14

Family

ID=30683491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12477484U Pending JPS6140761U (en) 1984-08-16 1984-08-16 PLL circuit

Country Status (1)

Country Link
JP (1) JPS6140761U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294971A (en) * 1989-05-10 1990-12-05 Hitachi Ltd Disk reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294971A (en) * 1989-05-10 1990-12-05 Hitachi Ltd Disk reproducing device

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