JPS6251569U - - Google Patents
Info
- Publication number
- JPS6251569U JPS6251569U JP14393385U JP14393385U JPS6251569U JP S6251569 U JPS6251569 U JP S6251569U JP 14393385 U JP14393385 U JP 14393385U JP 14393385 U JP14393385 U JP 14393385U JP S6251569 U JPS6251569 U JP S6251569U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- reproducing
- clock
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 230000008929 regeneration Effects 0.000 claims 1
- 238000011069 regeneration method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案になるクロツク信号再生回路の
一実施例のブロツク系統図、第２図は記録装置の
一例のブロツク系統図、第３図は再生装置の一例
のブロツク系統図である。
６…デイスク、７…ＦＭ復調回路、８…ビツト
ＰＬＬ回路、９…信号処理回路、１０…データセ
パレータ、１１…デイレイ回路。
FIG. 1 is a block diagram of an embodiment of a clock signal reproducing circuit according to the present invention, FIG. 2 is a block diagram of an example of a recording device, and FIG. 3 is a block diagram of an example of a reproducing device. 6... Disk, 7... FM demodulation circuit, 8... Bit PLL circuit, 9... Signal processing circuit, 10... Data separator, 11... Delay circuit.
Claims (1)
して得られる時間軸変動成分を有する再生信号よ
り、クロツク信号を再生するクロツク信号再生回
路であつて、 再生信号よりデジタル情報信号を復調する復調
回路と、 この復調回路から出力されるデジタル情報信号
が供給され、所定の周波数の信号を出力する位相
・周波数同期回路と、 この位相・周波数同期回路から出力される信号
を遅延する遅延回路とから構成したクロツク信号
再生回路。[Scope of Claim for Utility Model Registration] A clock signal reproducing circuit for reproducing a clock signal from a reproduced signal having a time axis fluctuation component obtained by recording and reproducing a self-clock digital information signal, the clock signal reproducing circuit reproducing a clock signal from a reproduced signal having a time axis fluctuation component obtained by recording and reproducing a self-clock digital information signal, a demodulation circuit that demodulates; a phase/frequency synchronization circuit that is supplied with the digital information signal output from the demodulation circuit and outputs a signal of a predetermined frequency; and a delay that delays the signal output from the phase/frequency synchronization circuit. A clock signal regeneration circuit consisting of a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14393385U JPS6251569U (en) | 1985-09-20 | 1985-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14393385U JPS6251569U (en) | 1985-09-20 | 1985-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6251569U true JPS6251569U (en) | 1987-03-31 |
Family
ID=31054074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14393385U Pending JPS6251569U (en) | 1985-09-20 | 1985-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6251569U (en) |
-
1985
- 1985-09-20 JP JP14393385U patent/JPS6251569U/ja active Pending
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