JPH02294971A - Disk reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the need for adjustment of a free-run frequency by adding a PLL loop which adds a voltage phi1 corresponding to the difference between the free-run frequency of a VCO and the frequency of a reference signal to the VCO to a PLL circuit where a signal inputted from an EFM input terminal is taken as the reference signal. CONSTITUTION:The PLL loop which is added is provided with a reference oscillation circuit 1, a frequency-divider 2 and a frequency-divider 7 where the output from the VCO is inputted in the case that reference input is not executed to a 1st PLL loop. The voltage phi is inputted in the VCO 6 with the output from the frequency-dividers 2 and 7 through a phase comparator 3 and an LPF 4. On the other hand, in the case that the reference input is executed to the 1st PLL loop where an EMF is inputted from a terminal 12, the output from the reference oscillation circuit is inputted in the frequency-divider where the output from the VCO is inputted and the phase of the input signal of the phase comparator 3 is kept in the same state that the reference input is not executed to the 1st PLL loop so as to always add the voltage phi1 to the VCO. Therefore, the voltage phi1 corresponding to the deviation of the free-run frequency from the EMF signal is impressed and the PLL circuit whose leading-in time is short is obtained without adjusting the free-run frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry] The present invention relates to a disc playback device, and in particular, to a PT. ，
The present invention relates to a disc playback device in which the L free run frequency is not adjusted.

[Conventional technology]

In conventional disc playback devices, for example, 4II Kaisho 591
As described in Publication No. 24013, since the EFM signal inputted with respect to the period T of transmission relays 1 to 1 has a pulse period of 3T to 11T, the polarity inversion signal of the EFM signal and the signal of the voltage controlled oscillator are different from each other. Configure a PLL that performs phase comparison,
I was importing serial data.

[Problem to be solved by the invention]

The above conventional technology uses a voltage controlled oscillator (hereinafter referred to as vC○)
No consideration was given to variations in the free run frequency of the E F, which includes jitter etc. reproduced from the disc.
In order to make the frequency of the M signal fall within the lock range of the I) L L circuit and to reduce the steady phase error, there is a problem in that the free run frequency needs to be adjusted.

? An object of the invention is to provide a disc playback device that does not require free-run frequency adjustment.

[Means to solve the problem]

2.1] The target is based on the input signal from the EFM input terminal.
(P L I., which is used as the I! signal, adds a second PLL loop to the circuit that applies a voltage φ, corresponding to the difference between the free-run frequency fc of the VCO and the frequency fB of the reference signal, to vC○. , is achieved by applying the voltage φ1 to ■C○ both when there is no reference input of the first PLL loop and when there is a reference input.

In the present invention, this second PLL loop includes a reference oscillation circuit, a frequency divider that divides the output of the reference oscillation circuit, and, if the first pr, r-loop does not have a reference input, ,■
It has a frequency divider to which the output of CO is input, the outputs of these two frequency dividers are input to a phase comparator, and the voltage φ■ is input to VC○ through a low-pass filter. On the other hand, the first P
If the L T-loop has a reference input, the frequency divider to which the ■CO output of the second loop was input receives the reference input instead of the ■Co output. The output of the oscillator circuit is input, and the phase relationship of the signal input to the digit comparator is maintained the same as when there is no reference power in the 1st-P[, 2, loop. This results in
Even when the first PLL loop has a reference input, the voltage φ
1 is applied to vC○.

[Effect]

In the above configuration, when the disc is not in the playback state, when the voltage φ■ corresponding to the difference between the reference oscillation frequency fn and the free run frequency fC of vCO is applied to ■C○, P
The L L loop is locked and the VCO oscillates at frequency fn. At this time, a signal obtained by dividing the output of the reference oscillation circuit and a signal obtained by dividing the output of vCQ are input to the phase comparator, and the phase relationship between the two is determined by the input voltage of VC○ and the output frequency. The relationship is shown in Figure 2.

Next, when the disc is in the playback state and the EFM signal is input manually, the frequency divider to which the ■CO output with a frequency of 1゛B was input is changed to the output of the reference oscillation circuit with a frequency of fB instead of the ■CO output. can be switched to be done manually. As a result, the phase relationship between the two frequency divider outputs input to the phase ratio 11t unit is maintained, and the voltage φ is outputted to vCO without being affected by fluctuations in the E FM signal. Therefore, since the voltage φ1 corresponding to the deviation of the free run frequency from the EFM signal frequency is applied, it is possible to configure a PLL circuit with a short pull-in time without adjusting the free run frequency.

〔Example〕

Embodiments of a disc playback device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a PL, L circuit for generating a data strobe clock in a disk reproducing apparatus according to a first embodiment of the present invention. In the figure, 1 is a reference oscillation circuit, 2 is a frequency divider, 3 is a phase comparator, 4 is a low-pass filter, 5 is an adder, 6 is a VC○, 7 is a frequency divider, 8, 9
1 is a switch circuit, 10 is a phase comparator, 11 is a low-pass filter, and 12 is an EFM input terminal. An EFM signal reproduced from a disc (not shown) is input from an EFM input terminal 12 and applied to a phase comparator 10 when the disc reproduction apparatus is in a reproduction state. Furthermore, when the playback device is in a non-playback state, zero potential is at the EFM input terminal 12.
The signal is applied to the phase comparator 10 via. The oscillation output of ■c○6 is input to the other input terminal of the phase comparator 10, and is compared with the input from the EFM input terminal 12. This phase comparator 10 has 3'r to l. ]. -JZ of the EFM signal, which is an NRZ code with a period of T, compares the resociation and falling edges with the phase of the clock signal, and when the human power from the EFM human power terminal 12 is at zero potential, φ1 is output. be done. The output of the phase comparator 10 is
After the high frequency signal is filtered through the low-pass filter 1], it is added to the output of the low-pass filter 4 in the adder 5, and the output is input to vc6. The EFM input terminal 12, phase comparator 10, low-pass filter 11, and Vc○6 shown in ``2'' are a conventional PLL which performs evening lock generation for performing data streams 1 to lobes of a disc playback device. It consists of

FIG. 2 shows the input/output characteristics of the VCO 6. In Fig. 2, the free run frequency fC of vC○ is shown, whereas the period T of the reproduced EFM signal is the reference frequency 1/T.
It fluctuates around =4.3218MHz. The reference oscillation circuit 1 is 4. 3 2 ]. It oscillates stably at 8 M Ilz.

Switch circuits 8 and 9 operate when the disc is in playback mode.
The switch circuit 8 is on, the switch circuit 9 is off,
When the disc is not being played, the switch circuit 8 is turned off and the switch circuit 9 is turned on. Therefore, when the disc is in a non-reproducing state, the output of the reference oscillation circuit 1 is input to the frequency divider 2, and the frequency is divided by 1/N. Further, the output of ■C○6 is inputted to the frequency divider 7, and the frequency is divided by 1/N. The outputs of the frequency divider 2 and the frequency divider 7 are respectively input to a phase comparator 3, and the output of the phase comparator 3 is inputted to an adder 5 after its high frequency is cut off by a low-pass filter 4. , low-pass filter]1 output φ. After being added to V C (:)
Added to 6. Above reference oscillator circuit J, frequency divider 2 and 7
, phase comparator 3, low-pass filter 4 and VC○6 form a second loop. Therefore, the oscillation frequency on the reference oscillation circuit is 1/T? ．． The VCO6 oscillates at 3218MHz. At this time, the output of the adder 5 is the voltage φ13+φ■ shown in FIG. 2, and the output of the low-pass filter 4 is φ. In this way, by adding the voltage φ to the offset 1 to the human power voltage of the VCO 6 through the second loop, the free run frequency of the vC◯6 is automatically adjusted from fc to the reference frequency 1/T.

When the disc is in the playback state, the switch circuits 8 and 9 are switched, and the power of the frequency divider 7 is switched from the VCO 6 to the output of the reference oscillation circuit 1.

At this time, when r'+f switches to the playback state, VCO6
is oscillating at fB due to automatic adjustment, so frequency divider 7
The frequency of the signal input to the
It remains unchanged. Therefore, the phase relationship between the outputs of the frequency dividers 2 and 7, which serve as input sources for the articulator 3, continues to be maintained even when changing from the non-reproducing time to the reproducing time. The above phase relationship is
An error of only 1゛ at most, i.e. 1, / N x 1
．． Contains an error of 00% (N is the frequency division ratio). Therefore, the frequency division ratio N is set depending on the required accuracy. At this time, the output of the low-pass filter 4 is applied to the voltage φ,
The automatic adjustment function continues to work even during playback. Also,
During reproduction, the signals input to the phase comparator 3 are all supplied from the reference oscillation circuit, so they are not affected by the input signal from the EFM input terminal 12. Therefore, the output of the low-pass filter 4 becomes a stable output, and does not adversely affect the conventional PLL described in 2.

As described above, according to this embodiment, a PLL with a small steady-state phase error can be configured in a disc playback device without requiring free-run adjustment.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 3 is a block diagram showing the configuration of the disc playback head in this embodiment. In the figure, 1:3 is a PLL circuit, 15 is a disk, 16 is an optical pick-up amplifier, 18 is a preamplifier, 19 is a lobe circuit for data transmission 1, 20 is a signal processing circuit, and 21 is an I) / A conversion +! 1{, 22 is a servo circuit, 23 is a microcomputer, 24 is an audio output terminal, and 25 is a digital output terminal. The signal recorded on the disk 15 is reproduced by an optical pickup 16 and a preamplifier 18, and this signal becomes an EFM signal. This EFM signal is transmitted to the data strobe circuit 19.
and the P L Ll path 13 according to the present invention. In addition, in this embodiment, the changeover switch of the PLL circuit J3 (corresponding to the switch circuits 8 and 9 in FIG. 1,
(not shown) is ST from the microcomputer 23
It is controlled by a signal indicating the OP state. Therefore, automatic adjustment functionality similar to that of the first embodiment described with reference to FIG. 1 is obtained under the control of a microcomputer. Note that the signal indicating the S T O P #k state from the microcomputer 23 is normally required in order to perform CLv control in a disc playback device, so the signal indicating the S T O P #k state from the microcomputer 23 is transmitted without creating a new control signal. In Fig. 3, it is possible to control the
The clock generated by the PLL circuit 13 is sent to the data stream 1-lobe circuit 19, and the EFM signal reproduced from the disk 15 is shifted from 1 to lobe by this clock. The data strobed by the data strobe circuit 9 is subjected to digital signal processing by the signal processing circuit 20, and then output from the digital output terminal 25, and is converted into an analog signal by the D/C converter 2. and output from the audio output terminal 24. Incidentally, the servo circuit 22 is for controlling the optical pinocapter 16, the disk motor, and the like.

As described above, according to this embodiment, a data stream 1 to lobe circuit with good bit 1 error rate 1 can be obtained in the disk reproducing apparatus without requiring adjustment. In addition, the signal indicating the STOP state of the microcomputer 23 is also required in conventional disc playback devices, and there is no need to create a new one, and without increasing the circuit scale, the 1) L L circuit according to the present invention can be used. It is possible to control the

I will clarify. FIG. 4 shows a PLT, which generates a chronograph for the data stream 1-loaf of the disc playback device in this embodiment.
FIG. 2 is a block diagram showing the configuration of a circuit. In the figure, ]−
is a reference oscillation circuit, 3 is a phase comparator, 4 is a low-pass filter, 5 is an adder, 6 is VC○, ]0 is a phase comparator, ]1
12 is an EFM input terminal, 26 is a changeover switch, and 27 is a frequency divider. Here, EFM
The input terminal 12, the phase comparator 10, the low-pass filter 11, and the VCO 6 constitute a conventional PT,L circuit, as in the first embodiment described with reference to FIG.

The reference oscillation circuit 1 has the frequency 1-/T=4 of the EFM signal.
, 3 2 18 MHz. It oscillates at different frequencies, and the signal processing circuit of the disc playback device, the D/C converter (not shown), etc., uses a reference cloth and a sampling frequency f.
．． At the same time, a clock of the sun printer frequency f++ is sent to the phase comparator 3, and at the same time, a clock of i/T = 4.321-8 is sent to the changeover switch 2G.
M. A frequency different from l{z, for example 4. 233
6M. Ilz, provides evening rock. The selector switch 26 is set to D? When the disc is not being played, connect it to the output side of VCO 6, and when the disc is playing, as shown in ``2'',
, p 7 (, 14 operates to connect to the tarok side of the oscillation circuit 1. When the disc is not being played back, the frequency divider 2
7 frequency-divides the input by 98 to make it 44.1 KIlz, which is the same as the fs signal from the reference oscillation circuit 1, and inputs it to the phase comparator 3. The output of the phase comparator 3 has its high frequency cut off by a low-pass filter 4, and the voltage φ■ shown in FIG. 2 is sent to an adder 5. On the other hand, the output voltage of the low-pass filter 11 is
φ as in the case of the first embodiment described with reference to FIG.

It is. Therefore, the output of VCO6 is the reference frequency 1/
T = 4.321.8MI{z and oscillates. In other words, the free run frequency of VC○ is 1/T = 4.3
This means that the frequency is automatically adjusted to 218MHz. Further, for disk reproduction +1iy, the frequency divider 27 divides the clock from the reference oscillation circuit 1 to the sampling frequency fs.

- As an example, if the evening lock sent is 4. 2336 M
In the case of Hz, divide by 96 and divide by 44. ]-K.H.
Outputs the z signal. The switching of the frequency division ratio of the frequency divider 27 and the switching of the switching switch 26 are controlled by a control microcomputer (not shown) in the disc playback device. , the phase relationship of the signals sent to the phase comparator 3 is the reciprocal of the frequency division ratio during disk playback, that is, in our example, ]/96x+. O
Within an error range of 0%, hold the test in the same way as when it is not being played back. Therefore, the output of the low-pass filter 4 continues to output the voltage φ, without being affected by the incoming signal from the EFM input terminal 7-12. If the frequency is changed to 1/i'', the free run frequency of the VCO 6 is automatically adjusted to the arbitration frequency 1/i'' even during disk reproduction.

As described above, according to this embodiment, the oscillation frequency of the reference oscillation circuit 1 does not need to be the same as the reference frequency 1/T. Further, according to this embodiment, the reference oscillation circuit 1 is
It can be used in common with other clock reference clock generation circuits used in signal processing circuits of disk playback devices, etc. Further, according to this embodiment, by switching the frequency division ratio of the frequency divider 27, the number of frequency dividers, that is, the circuit scale of the frequency divider can be reduced.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a block diagram showing the configuration of a 1-'LL circuit that generates clocks for data stream 1 and lobe of the disc reproducing apparatus in this embodiment. The block diagram shown in FIG. 5 shows that the signal sent from the reference oscillation circuit 1 to the phase comparator 3 is not a signal with a frequency fs but a signal with a frequency f0-, and that the dividing ratio of the frequency divider 27 is , the divided output is f0
．． The configuration is the same as in FIG. 4, except for how it is selected. Here, the frequency f. z is the reference frequency 1.
/T and the frequency of the signal sent from the reference oscillation circuit to the frequency divider 27 may be any common divisor. For example,
Reference frequency 1/T = 4.3218MHz, the frequency of the signal from the reference oscillation circuit 1 to the frequency divider 27 is 4. 2
When it is 336 MHZ, fω=11.025K
You can choose IIz.

At this time, the frequency division ratio of the frequency divider 27 is 245 when the disc is not being reproduced, and 240 when the disc is being reproduced. Furthermore, the error that occurs in the phase relationship of the phase comparator 3 when the disc is not being played back and is being played back is 0.4%. Other operations are the same as those in the third embodiment described with reference to FIG.

As described in 2 below, according to this embodiment, the oscillation frequency of the reference oscillation circuit 1 is set to the reference {IH frequency 1. There is no need to make it the same as /T. Further, the reference oscillation circuit can be used in common with other Tarosota reference evening lock generation circuits such as the signal processing circuit of a disc playback device. Furthermore, by switching the frequency division ratio of the frequency divider 27, the circuit scale of the frequency divider can be reduced. Further, according to this embodiment, the accuracy of automatic adjustment of the free-run frequency can be selected to a certain level.

FIG. 6 shows a circuit diagram of an example in which the phase comparator 10 and the low-pass filter 11 shown in FIGS. 1, 4, and 5 are specifically implemented. In FIG. 6, 6]. ,62
is an Ex NOR circuit, 63-65 is a flip-flop circuit, and 66. 67 is an in-harter circuit, 68 is a ■] channel MOSEFT, and 69 is an N-channel MOSEI.
” T. In this way, the phase comparator and low-pass filter can be realized with a small-scale circuit.

〔Effect of the invention〕

・16 The free-run frequency of ■C○ of the PLL circuit in the data storage circuit can be automatically adjusted to a frequency of 1/T for the input signal transmission rate 1. This has the effect of facilitating coordination.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLL circuit for generating a clock for data strobe of a disc playback device in a first embodiment of the present invention, FIG. 2 is a characteristic diagram for explaining the embodiment, and FIG. A block diagram showing the configuration of a disc playback device according to a second embodiment of the present invention, FIG.
Block diagram of the PLL circuit for data stream 1 lobe clock generation of the disc playback device in the embodiment of 5th
The figure shows the same < P L L in the fourth embodiment of the invention.
The block diagram of the l path, FIG. 6, is shown in Section 1.4. FIG. 5 is a circuit diagram showing a specific example of the phase comparator and low-pass filter in FIGS. 1...Reference oscillation circuit, 2. Frequency divider, 3.
Place A/E comparator, 4. Low pass filter, 5.
Adder, 7. Frequency divider, 10.. Phase comparator, 26.. Switching switch, 6-V CO, 8, 9.. Switch circuit, 11.. Low pass filter, 27. Frequency divider.

Claims (1)

[Claims] 1. A means for rotating a disk, an optical pickup for detecting a serial signal from the disk, a data strobe circuit for capturing a serial signal output from the optical pickup, and a means for detecting a serial signal output from the data strobe circuit. A disc playback device comprising a signal processing circuit that performs signal processing of digital signals, a reference signal oscillation circuit that controls the signal processing circuit and disc rotation means, and a voltage controlled oscillator whose output frequency is controlled by voltage; a first phase comparator that compares the phases of the output of the voltage controlled oscillator and the reproduced serial digital signal from the optical pickup; and a high frequency component of the output of the first phase comparator is cut off; a PLL loop including a first low-pass filter outputting to the voltage controlled oscillator; a frequency divider, a second frequency divider that divides the output of the voltage controlled oscillator or the output of the reference signal oscillation circuit, and an input of the second frequency divider;
a switching circuit that switches between the voltage controlled oscillation circuit and the reference signal oscillation circuit; a second phase comparator that compares the phases of the output of the second frequency divider; and the second phase comparator. a second low-pass filter that cuts off high-frequency components of the output of the second low-pass filter;
1. A disc playback device comprising a PLL circuit including an adder that adds to an LL loop. 2. The disk playback device according to claim 1, characterized in that the switching circuit is configured to be switched to the reference signal oscillation circuit side while the disk is rotating, and to the voltage controlled oscillation circuit side at other times. Device.