JPS62257676A - Compact disk player - Google Patents

Abstract

PURPOSE:To change the reproducing speed of a CD only with the operation of a switch or a volume by varying a self running frequency of a VCO of a PLL circuit, an oscillated frequency of a master clock generator by the switch of the volume of a speed selection circuit. CONSTITUTION:In turning a switch of a speed selection circuit 20 to the position (b), the switch of the PLL circuit 51 and the switch of the master clock generator 71 are turned respectively to the position (b) and a CD 1 is reproduced by the same fequency and the same speed as those of a conventional player. In turning the switch of the circuit 20 to the position (a), the switch of the PLL circuit 51 and the switch of the master clock generator 71 are turned respectively to the position (a), and the clock frequency is doubled. Since a closed loop comprising a phase comparator 8, a motor servo circuit 9, a motor 10, the CD 1, a pickup 2, a waveform shaping circuit 4 and the PLL circuit 51 constitutes a PLL, the clock component of an EFM signal read from the pickup 2 has a double frequency. Thus, the EFM signal is reproduced by the double speed and the CD is reproduced by a double speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CD player that can arbitrarily change the playback speed of a compact disc (hereinafter referred to as a CD).

[Conventional technology]

Conventionally, there has been a CD player as shown in FIG.

In the figure, l is a CD, 2 is a pick amplifier, 3 is a tracking/focus servo circuit, 4 is a waveform shaping circuit,
5 is a PLL circuit, 6 is a demodulation circuit for demodulating the digital signal, 7 is a mask crofter generator, 8 is a phase comparator for comparing the phase of the output clock of the PLL circuit 5 with the master clock, 9 is a motor 10 11 is a digital signal processing circuit; 12 is a motor servo circuit for controlling the
13 is a D/A converter (hereinafter referred to as DAC) for converting audio digital signals into PAM signals, 13 is a deglitcher for removing glitches and separating L and R signals, and 14 is a PAM signal converter. A low pass filter (hereinafter referred to as LPF) for converting into an analog signal, and 15 a de-emphasis circuit.

The laser beam output from the pink-up 2 is reflected by the CDI and input to the pickup 2, and after being waveform-shaped by the waveform shaping circuit 4, it is output to the PLL circuit 5 and the demodulation circuit 6. This signal is an EFM signal.

The PLL circuit 5 reproduces the clock of the EFM signal. Using this clock as a reference, the demodulation circuit 6 demodulates a digital signal from the EFM signal and outputs the digital signal.

The digital signal processing circuit 11 operates with the master clock output from the master clock generator 7, performs deinterleaving, error correction, etc., and converts the audio digital signal to the DAC 1.
Output to 2. It also outputs a deglitch signal to the deglitcher 13 and a signal indicating the presence or absence of emphasis to the de-emphasis circuit 15, respectively.

The DAC 12 outputs an analog signal (PAM signal) corresponding to the input digital signal to the deglitcher 13. Glitches are removed from the PAM signal in the deglitcher 13, the L signal is separated into the R signal, and the LPF 14
The PAM signal is interpolated, becomes an analog signal, and is output to the de-emphasis circuit 15.

In the de-emphasis circuit 15, a signal indicating the presence or absence of emphasis applies de-emphasis to the input analog signal if it is "present", and outputs it without applying de-emphasis if it is "absent".

Note that the phase comparator 8 compares the phases of the clock reproduced by the PLL circuit 5 and the master clock, and outputs a voltage corresponding to the phase difference to the motor servo circuit 9. The motor servo circuit 9 controls the rotational speed of the remoter 10 using the above voltage.

In other words, a closed loop consisting of a phase comparator 8, a motor servo circuit 9, a motor 10, a CDI, a pink-up 2, a waveform shaping circuit 4, and a PLL circuit 5 is a PLL (phase-locked loop) with the mask cropper as an input. It has become. Therefore, the clock component of the EFM signal read out from the pickup 2 is controlled to always be constant.

[Problems to be solved by the invention]

However, since the conventional CD player is configured as described above, it is not possible to change the frequency of the master clock and the free-running oscillation frequency of the VCO of the PLL circuit.

Therefore, there was a problem in that the playback speed of the CD could not be changed.

[Purpose of the invention]

An object of the present invention is to overcome the problems of the above-mentioned conventional techniques, and to change the playback speed of a CD by changing the master clock frequency and the free-running oscillation frequency of the vCO of the PLL circuit. The object of the present invention is to provide an improved CD player.

[Summary of the invention]

That is, the present invention provides means for selecting the playback speed of a compact disc and connects its output to the PLL circuit and the master clock generator, thereby adjusting the free-running oscillation frequency of the VCO of the PLL circuit and the master clock frequency of the master clock generator. It is characterized by being configured to change.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram of a CD player according to an embodiment of the present invention.

In the figure, 1 to 4, 6, and 8 to 15 have the same configuration as in FIG. 2.

What is unique to this invention is as follows.

20 is a speed selection circuit that specifies the CDI playback speed as standard speed or double speed; 51 is a VCO 2 that oscillates at the same free-running oscillation frequency as the vCO of the conventional PLL circuit 5; and a VCOI that oscillates at twice the frequency. and a switch for switching the outputs of these two VCOIs 2 by the output of the speed selection circuit 20; 71 is a master clock generation circuit that oscillates at twice the frequency of the conventional master clock generator 7; This master clock generator is composed of a frequency divider circuit and a switch that switches between the output of the master clock generation circuit and the output of the frequency divider circuit according to the output of the speed selection circuit 20.

Next, the CD playback speed switching operation will be explained.

Now, when the switch of the speed selection circuit 20 is set to the b side, P
The switch of the LL circuit 51 and the switch of the master clock generator 71 are also set to the b side, so that the same frequency as the conventional one is outputted, and CDI is reproduced at the same speed as the conventional one.

When the switch of the circuit 20 is set to the a side, the switches of the PLL circuit 51 and the mask clock generator 71 are also set to the a side, resulting in a clock having twice the frequency of the conventional clock.

At this time, the closed loop consisting of the phase comparator 8, motor servo circuit 9, motor 10, CD 1, pickup 2, waveform shaping circuit 4, and PLL circuit 51 constitutes a PLL, so the EFM signal read from the pickup 2 is The clock component will have twice the frequency compared to the conventional one. That is, the EFM signal is reproduced at twice the speed compared to the conventional method.

Therefore, CDs can be played back twice as fast as in the past.

Note that the number of PLL circuits 51 (7) and VCO may be reduced to one, and the constants of the components that determine the oscillation frequency may be changed.

Further, the speed may be the standard speed or a speed other than the standard speed, and is not limited to the double speed.

Further, three or more types of speeds may be varied.

Further, by using a volume in the speed selection circuit 20, the free-running oscillation frequency of the VCO of the PLL circuit 51 and the oscillation frequency of the master crofter generator 71 can be changed continuously.

Further, in addition to the vCO of the PLL circuit 51 and the oscillation frequency of the masked clock generator 71, LPFs having different cutoff frequencies may be switched to change the de-emphasis characteristic of the de-emphasis circuit 15. in this case,
Even if the CD playback speed is changed, all the information of the playback analog signal can be correctly output.

Furthermore, instead of the switch of the PLL circuit 51, a frequency divider may be provided at the output of the VCO, and the frequency division ratio of the frequency divider may be changed by the speed selection circuit 20.

Further, the master clock generator 71 may be configured with a mask crofter generation circuit and a variable division ratio frequency divider, or may be configured with a plurality of mask crofter generation circuits having different oscillation frequencies.

〔Effect of the invention〕

As explained above, according to the present invention, v of the PLL circuit
Since the free-running oscillation frequency of Co and the oscillation frequency of the master clock generator are configured to be changed by a switch or a volume in the speed selection circuit, the CD playback speed can be changed simply by operating the switch or volume. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CD player according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional CD player. 1...CD, 11...digital signal processing circuit, 2
0... Speed selection circuit, 51... PLL circuit, 71.
...Master clock generator.

Claims (1)

[Claims] For selecting the playback speed of a compact disc in a compact disc player having a PLL circuit for extracting a clock component from a waveform-shaped signal and a master clock generator for generating a reference clock for digital signal processing. By providing speed selection means and connecting the output of the speed selection means to the PLL circuit and the master clock generator, the PLL
A compact disc player characterized in that the free-running oscillation frequency of the VCO of the circuit and the reference clock frequency of the master clock generator are changed.