JPS61204872A - Pitch control circuit for cd player - Google Patents

Abstract

PURPOSE:To vary a pitch stably in a wide range by changing the free running frequency of a VCO of a reproducing clock circuit while following up the frequency of reference clocks. CONSTITUTION:In case of pitch control, the reference clock having a frequency set by a pitch control knob 34 is outputted from a VCO 32 and is inputted to a phase comparator 22 through a switch 36 and a 1/2 frequency dividing circuit 37, and a disc rotation PLL servo is so operated that the phase of a reproduced clock 22 coincides with that of this reference clock. Since the free running frequency of a VCO 30 of a clock reproducing circuit 14 is set to the same value as the reference clock of the VCO 32 at this time, the lock state is attained stably in the PLL circuit. Thus, the pitch is varied stably in a wide range.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit for variable control of pitch (sound height) during playback in a CD (compact disc) player, and is an improvement over the conventional one. It is designed to provide stable operation and a wide variable range.

[Conventional technology]

In recent years, karaoke machines using CD players have appeared. This has advantages over conventional tapes, such as faster selection of songs and better sound quality. However, as explained below, conventional CD karaoke machines do not have pitch control, which is one of the important functions for karaoke machines, that is, the ability to arbitrarily change the pitch according to the height of the singer's keys. It was difficult to implement, and either there was no pitch control function at all, or even if it was included, the variable range was narrow and insufficient.

FIG. 2 shows a disk rotation control circuit in a conventional CD player. Recorded information on the disk 10 is detected by an optical head 12, and the detection signal (EFM signal) is input to a clock reproduction circuit 14. The clock regeneration circuit 14 generates a regenerated clock having a period corresponding to one channel bit of the EFM signal and synchronized in phase with the EFM signal. That is, the phase error detection circuit 16 detects the FFM signal and the VCO (voltage controlled oscillator>20
The output signals of the two are compared and a signal with a pulse width corresponding to their phase error is output. This signal is low pass filter 1
8 and is input to V C020 to control its oscillation frequency. The output signal of the VCO 20 is fed back to the phase error detection circuit 16. This gives v 'c 020
A reproduced clock having a period corresponding to one channel bit of the EFM signal and phase-synchronized with the EFM signal is output from.

The reproduced clock is transmitted to the crystal oscillator 2 in the phase comparator 22.
4, and the phase comparator 22 outputs a signal with a pulse width corresponding to the phase difference.

This signal is smoothed by a low-pass filter 25 and applied to the disk motor 28 via a drive amplifier 26. In this way, the disk rotation control circuit of FIG. 2 as a whole constitutes a PLL-control loop in which the VCO is replaced with the disk motor 28.
The rotation speed is controlled so that the regeneration 1] is synchronized with the reference clock from the crystal oscillator 2/I, and as a result, CL V (Con5tant Linear Vel
city) control is realized.

In conventional CD players, when changing the pitch,
For example, a variable frequency oscillator is used in place of the crystal oscillator 24, thereby changing the frequency of the reference clock. In other words, if you change the frequency of the reference clock,
The rotation speed of the disc changes so that the playback clock follows this, and the hip changes. For example, if the frequency of the reference clock is lowered, the rotational speed of the disk motor 28 will be lowered, and the pitch will be lowered. Conversely, if the frequency of the reference clock is increased, the rotational speed of the disk motor 28 becomes faster and the bit becomes higher.

However, as shown in Fig. 3, this PLL control has a hold-in range (holding range), a capture range (
4, where the pull-in range) is the free run frequency of the VCO20,
The frequency is set within a certain range centered around 3218 MHz, and cannot be set over a wide range due to circuit design constraints and variations. Furthermore, if the sharpening range is too wide, problems such as increased stabilization time and side lock may occur. For this reason, the hold-in range, "capture" arrangement, is selected within a range of several percent around 4.3218M)-1z. Therefore, if the frequency of the reference clock is changed significantly for the purpose of changing the bit, the P
I' I-control becomes unlocked, a reproduced clock cannot be obtained, the disk rotation servo malfunctions, and in extreme cases, rotation stops. Therefore, the conventional CD
In players, even if pitch control was attempted, the variable range was narrow (at best, it could be done within the bold-in range, and it was insufficient to change the chromatic pitch (generally speaking, A frequency change of approximately 6% is required to change the chromatic pitch.)
.

[Problem that the invention seeks to solve]

This invention solves the drawbacks in the conventional techniques, and
The present invention aims to provide a pitch control circuit for a C[) player that provides stable operation and a wide variable range.

[Means for solving problems]

In this invention, the rerun frequency of the VCO in the clock recovery circuit is changed in accordance with the change in the reference clock frequency.

[For production]

According to the solving means of the present invention, the hold-in range and capture range of the disk rotation PLL Leevo loop also move as the reference clock frequency changes, so that the reference clock frequency is always within the range of the hold-in range and the capture range. PL can be stably maintained even when the reference clock frequency is varied over a wide range.
A locked state of the L circuit is obtained.

〔Example〕

An embodiment of this invention is shown in FIG. In Figure 1,
Recorded information on the disc 10 is detected by an optical head 12,
The detection signal (EFM signal) is input to the clock recovery circuit 14. In the clock regeneration circuit 14, a phase error detection circuit 16 compares the FFM signal and the output signal of the VCO 30, and outputs a signal with a pulse width corresponding to the phase difference between them. The signal is smoothed by a low-pass filter 18 and
It is input to CO 30 and controls its oscillation frequency. V
The output signal of C03,0 is fed back to the phase error detection circuit 16. This causes 1 of the EFM signal from VCo, 30.
A reproduced signal having a period corresponding to a digital bit and phase synchronized with the EFM signal is output. The recovered clock is used to time the RAM write operation, which is a temporary storage area for decoder dynamics and jitter absorption. Note that the free run frequency of the VCo 30 can be varied around 4.3218M)-1z.

The crystal oscillator 24 outputs a signal of 4.3218M1-lz. This signal is used as a reference clock when pitch control is not performed (when reproducing at standard pitch). The VCO 32 outputs the Wt% clock when performing pitch control.
The oscillation frequency is changed around 4.3218M')-1z. The vC030 and vC032 are controlled in conjunction with each other by the pitch controller 1 to the roll knob 34, and the free run frequency or oscillation frequency is variably controlled while maintaining approximately the same value.

The switch 36 is used to select either the output of the crystal oscillator 24 or the output of the VCO 32 as the reference clock, and is connected to the crystal oscillator 24 side when not performing pitch control, and when performing pitch control 1 to roll. is connected to the VCO32 side. This switching of the switch 36 is performed based on the detection of the midpoint position of the pitch control knob 34. In other words, the reference pitch instruction when the pitch control knob 34 is at the midpoint position is as follows.
The switch 36 is connected to the crystal oscillator 24, and when in any other position (pitch control instruction), the switch 36 is connected to the VCO 32.

The reference clock output from the switch 36 is used for reading operations from the RAM, which is a temporary storage area for absorbing jitter.

The phase comparator 22 compares the phases of the reproduced clock and the reference clock, and outputs a signal with a pulse width corresponding to the phase difference. This signal is smoothed by a low-pass filter 25 and drives a disk motor 28 via a drive amplifier 26.

The P L 1 rotation control loop is configured as described above.

The pitch control operation by the circuit shown in FIG. 1 will be explained with reference to FIGS. 4 to 6. Here, a case is shown in which the pitch is varied by, for example, ±10% with respect to the standard pitch.

When playing back at the standard pitch, set the pitch control knob 34 to the midpoint position. This allows VCO3
The free run frequency of 0 is set to the standard 4.3218MHz. Further, the switch 36 is connected to the crystal oscillator 24 side, and a reference clock of 4.3218 MHz is output.

FIG. 4 shows the characteristics of the F)IL control loop at this time. 1", that is, bold in range,
The virtual range is 4.321 of the reference clock frequency.
8M1-(determined in the range centered on z.

Therefore, the PLL control loop is stably locked, and reproduction is performed at the standard pitch.

Turning the pitch control knob all the way to the left changes the 7-run frequency of VCP30 and the VCO32 (
7) The oscillation frequency is set to 3.8896 MHz, which is 10% lower than 4.3218 MHz.

At this time, the switch 36 is connected to the VCO 32 side. As a result, the reference clock becomes 3.8896 MHz.

Further, as shown in FIG. 5, the PLL control loop has a hold-in range and a capture range determined within a range centered on the reference clock frequency of 3.8896 MH2. Therefore, the PLL control loop is stably locked around 3.8896 MHz, and is reproduced at a pitch 10% lower than the standard.

When the pitch control I-roll knob 34 is turned all the way to the right, the free run frequency of the vcoao and the VC
The oscillation frequency of O32 is set to 4.7540 Ml-1Z, which is 10% higher than 4.3218M I-1z.

At this time, the switch 36 is connected to the VCO 32 side.

To this, J: The reference clock is 4.7'540M1-1
7. Howl. Further, as shown in FIG. 6, in the Pl-1 control loop, the bold-in range and the cab du range are determined in a range centered on the reference clock frequency of 4.75'40 MHZ.

Therefore, the PLL control loop stably obtains a one-knock state and is reproduced at a pitch 10% higher than the standard.

As described above, in the PLL control loop shown in Fig. 1, the bold-in range and cab du range are determined around the constantly changing frequency of the reference clock, so a locked state can be obtained over a wide range, and the pitch can be stabilized over a wide range. can be changed.

Here, a specific example of the embodiment shown in FIG. 1 is shown in FIG.

In the phase error detection circuit 16 shown in FIG.
1 to L4 are the 1/2 frequency dividing circuit 4 for the output signal of the VCO 30.
Edges 1 to 1 are triggered by the reproduced clock φ1 and φ, which are obtained by dividing the frequency by 1/2 by 0. Regenerated clocks φJ and φ are two-phase clocks whose phases are shifted by 172 cycles from each other.
J is the latch circuit L1. clock ψK
is input to the latch circuit 12.14. Therefore, the latch circuits 1-1 to 1-4 are driven alternately by the clocks φJ and φ, and the EFM signal is 1/2 of the clock φJ, φ.
It is sequentially shifted by the phase difference of the period.

The exclusive OR circuit EXORI inputs the original signal SO and the output S1 of the first stage latch circuit L1, and generates a pulse signal P1 at the rise and fall of the EFM signal waveform with a width corresponding to their phase difference. Output.

Further, the exclusive OR circuit EXOR2 outputs the output S3 of the third stage latch circuit L3 and the output S4 of the fourth stage latch circuit L4.
is input, and a pulse signal P2 is output with a width corresponding to the phase difference between the rising and falling edges of the waveform of the EFM signal.

According to this configuration, the phase difference between the output S3 of the latch circuit L3 and the output S4 of the latch circuit L4 is always exactly half the period of the clocks φJ and φ, so the pulse width of the pulse signal P2 is The width is half a cycle of clocks φJ and φ. On the other hand, the output S1 of the input SO latch circuit L1
The phase difference between the input EFM signal SO and the clocks φJ and φ changes depending on the phase difference between the input EFM signal SO and the clocks φJ and φ, and the pulse width of the pulse P1 changes within the length of one cycle of the clocks φJ and φ.

Outputs P1. of exclusive OR circuits EXOR1 and EXOR2. ”
P2 is applied to the gates of FET1.2, respectively.

FFT1 and 2 are powered by V. It is connected in series between FETI and ground, and the output VO is taken out from the midpoint between FETI and FETI. Therefore, the output VO is V when only FET1 is turned on. However, when only FET2 is turned on, the input side of exclusive OR circuits EXOR1 and EXOR2 is connected to latch circuit L2. Since they are separated at L3, F
ET1.2 are never turned on at the same time.

With the above configuration, the phase y difference detection circuit 16 outputs two pulses, an upward pulse at the VDO level and a downward pulse at the 0 volt level, each time the waveform rises or falls. At this time, the downward pulse always has a pulse width of 1/2 period of the recovered clock φJ, φ, but the upward pulse has a pulse width of 1/2 period of the recovered clock φJ, φ, depending on the phase error between the EFM signal and the recovered clock φJ, φ. It varies within the length of one cycle.

The release OR circuit EXOR3 outputs an EFM reproduction signal by inputting the output S2 of the second stage latch circuit L2 and the output S4 of the fourth stage latch circuit L4.

The output signal ■o of the phase error detection circuit 16 is smoothed by the low-pass filter 18, and is then combined with the EFM signal and the reproduced clock φJ.
, φ, this DC voltage is input to the VCO 30 in accordance with the phase error in φ. The VCO 30 is composed of an Ic oscillation circuit, and the inverter 41 causes oscillation by an inversion action.

The VCO 30 includes a varactor diode 42, and the capacitance is changed by a voltage applied via a volume 44 interlocked with the pitch control knob 34, thereby changing the free run frequency. The oscillation frequency is controlled by the voltage from the low-pass filter 18.

The output signal of the VCO 30 is frequency-divided by 1/2 by a 1/2 frequency divider circuit 40 to generate reproduced clocks φJ and φ, and is fed back to the phase error detection circuit 16. In this way, the oscillation frequency of the VCO 30 is controlled so that reproduced clocks φJ and φK having a period equivalent to 1 V channel bit of the EFM signal and synchronized with the EFM signal are obtained.

FIG. 8 shows the operation of the clock recovery circuit 14 shown in FIG. 7.

The latch circuits L1, , L3 operate at the timing of the clock φJ, and the latch circuits L2, . L4 is driven accurately at the timing of clock φ.

Therefore, regardless of whether the input FFM signal SO is ahead or behind the phase, the latch circuit [
It is latched to 1. Similarly, the output S of latch circuit 1-1
1 is latched by the latch circuit L2 at the clock φ, and the output S2 of the latch circuit L2 is latched by the latch circuit L3 at the clock φJ.
The output S3 of the latch circuit L3 is latched by the clock φ
The signal is latched by the latch circuit 1-4. In this way, the clock φJ is always sent to the latch circuits L2→L3→L4.

The EFM signal is transmitted with a phase difference of half a cycle from φ.

The exclusive OR circuit EXOR2 inputs the output of the latch circuit L3゜L4) js3.84, so its output P2 is 1''
The time width is always constant and corresponds to a half cycle of the clocks φJ and φ. On the other hand, exclusive OR circuit EXORI has input E
Since the FM signal SO and the output S1 of the latch circuit L1 are input, the time width for which the output P1 becomes 1'' is equal to the input EFM.
It varies within one cycle of clock φJ depending on the phase difference between the rising and falling edges of signal SO and clock φJ.

In the input EFM signal SO in FIG. 8, the solid line indicates a state in which the phases are exactly matched. When this = 15 -, the output P1 of the exclusive OR circuit EXOR1 is
Since the time width of II is half the period of the clocks φJ and φ, the midpoint voltage of FETs 1 and 2 is 0, as shown by the solid line in Figure 8, where the upper and lower pulses have the same width. , which can be obtained by smoothing the clock φ
When the frequency of the input EFM signal SO decreases with respect to J and φK, the input EFM signal S
Since the phase of O is delayed, exclusive OR circuit EXOR1
The time period during which the output P1 becomes 1'' becomes shorter. At this time,
The output P2 of exclusive OR circuit EXOR2 is II I II
The time width of the roar is clock φJ.

Since the half cycle of φ remains, the output of FET1.2 is
For O, the upper pulse has a shorter time width than the lower pulse. Therefore, the control voltage of the VCO 30 decreases in the direction of O, and the oscillation frequency of the VCO 30 decreases to follow the frequency decrease of the input EFM signal SO.

Conversely, for clocks φJ and φK, input EFM signal S
As the frequency of O increases, as shown by the dotted line in Figure 8,
Since the phase of the input EFM signal SO advances, the time during which the output P2 of the exclusive OR circuit EXOR2 is "1" becomes longer. At this time, the output P2 of the exclusive OR circuit EXOR2
Since the time width when is 1'' remains half the cycle of the clocks φJ and φ, the upper pulse of the output VO of FETI and 2 has a longer time width than the lower pulse. Therefore, The control voltage of the VCO 30 increases in the direction of VDD, and the oscillation frequency of the VCO 30 increases to follow the increase in frequency of the input FEM signal SO.

The clock recovery circuit 14 operates as described above.

In FIG. 7, a VCO 32 is constructed in the same manner as the VCO 30, and is controlled by a voltage applied to a varactor diode 46 via a regulator 44 that is linked to a pitch control knob 44, and is the same as the 7-run frequency of the VCO 30. The oscillation frequency is set in Frequency. Therefore, when performing pitch control, use the pitch controller l.
- A reference clock with a frequency set by the roll knob 34 is output from the VC032, and this It tp clock is input to the phase comparator 25 via the switch 36 and the 1/2 frequency divider 37, and the phase of the reproduced clock 22 is This I
The disk rotation PLL servo works to match the f clock. At this time, since the free run frequency of V'C'03'0 of the clock regeneration circuit 14 is set to the same frequency as the VC032 reference clock, the PLL
The circuit can be stably locked. Therefore, the pitch can be stably varied over a wide range.

(Example of modification) In the above embodiment, the switch 36 is automatically switched by detecting that the pitch control 1-roll knob 34 is at the middle position, but the pitch control and switching of the switch 36 are made independent. But that's fine. In that case, when the switch 36 is connected to the crystal oscillator 24 side, the control voltage supply line to the varactor diode 42 in the clock regeneration circuit 14 is cut in the middle, etc., resulting in an unnecessary disconnection to the output regeneration circuit 14 side. Avoid applying voltage.

Further, in the above embodiment, the free run frequency of the VCO 30 was made to match the oscillation frequency of the VCO 32, but it is not necessary to do so. , the 7 rerun frequency of the VCO 30 may be changed so that it is included in the lock range.

〔Effect of the invention〕

As explained above, according to the present invention, since the rerun frequency of the VCO of the regenerated clock circuit is changed in accordance with the frequency of the reference clock, the frequency of the reference clock can be changed over a wide range. It is possible to stably obtain a locked state of the disk rotation servo even if the disk rotation servo is avoided, and the pitch can be varied stably over a wide range and with a simple configuration.
It can be effectively used in karaoke equipment, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a disk rotation control circuit of a conventional CD player. FIG. 3 is a miniature diagram showing the characteristics of the control circuit of FIG. 4 to 6 are diagrams showing how the characteristics of the disk rotation control circuit shown in FIG. 1 change. FIG. 7 is a circuit diagram showing a detailed example of the disk rotation control circuit of FIG. 1. FIG. 8 is an operational waveform diagram of the clock recovery circuit 14 of FIG. 7. 14... Clock regeneration circuit, 30... vCo132 in clock regeneration circuit 14... VC for reference clock generation
0, 34... Pitch control knob, 36...
・Reference clock switching switch, 42...Varactor diode for free run frequency variation, 44...Pitch"
Control volume, 46... Varactor diode for variable reference clock frequency. 1, saki-r't→ itosa α ~ C) CJ (J“ 〉
〉C) ゝ ゝ, , Mgu- no \
ward must be ゞ80・ku), +[0ψC) kuf-be. Total 1 加P″□ ” J ＼゛゛

Claims (1)

[Claims] The invention is characterized by comprising: means for changing the frequency of a reference clock; and means for changing the free-run frequency of a VCO that creates a reproduced clock from an EFM signal in accordance with the reference clock. CD player pitch control circuit.