JPS6111973A - Reproduction phase locked control circuit of self-synchronizing clock - Google Patents

Abstract

PURPOSE:To allow phase locked control over a reproducing signal to follow up variation in reproducing speed even if the reproducing signal has a dropout, etc., during the variation in reproducing speed by utilizing a control valtage as a reverse bias voltage which controls the oscillation frequency of a clap type LC oscillation circuit of a PLLVCO (phase-locked) loop voltage-controlled oscillation) circuit. CONSTITUTION:The control voltagr Vc is utilized as the reverse bias voltage which controls the oscillation frequency of the clap type LC oscillation circuit 194f of the PLLVCO circuit 194. The operation point of the PLLVCO circuit 194 is settable to an almost optimum point regardless of variation in reproducing speed, and consequently a lock range and a capture range can be equal in width above and below the frequency at the time of synchronism. Therefore, the self- synchronizinf clock reproducing PLL circuit performs phase locked control following up variation in the transmission speed of an input signal SDI all the time even if the variation is large, and a trouble point from a stepout due to a dropout of the playback signal SRF to the acquisition of synchronism is eliminated.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital information signal reproducing device having a variable playback speed function, such as a CAD (digital audio disc) reproducing device, and particularly relates to a digital information signal reproducing device having a variable playback speed function, such as a CAD (digital audio disc) reproducing device, and particularly to This invention relates to an improvement in a self-synchronized clock reproduction phase synchronization control circuit that generates a clock signal and controls the phase of a reproduced signal using this clock signal.

[Technical background of the invention and its problems] Recently, in the field of audio equipment, PCM (pulse code modulation) is being used to achieve as high fidelity reproduction as possible.
By using technology, a digital information signal obtained by PCM modulating an audio signal is recorded on a recording medium such as a disk or magnetic tape, and this recording medium is reproduced and demodulated to obtain an audio signal with extremely little deterioration. Digital information signal reproducing apparatuses that can reproduce digital information are becoming popular.

These digital information signal reproducing apparatuses have recently been equipped with a reproduction speed variable function, and attempts have been made to make it possible to freely vary the tempo of reproduced sound by varying the reproduction speed.

Here, the general structure of a digital information signal reproducing apparatus having the variable reproduction speed function as described above will be explained by taking an optical digital audio disc reproducing apparatus shown in FIG. 5 as an example.

That is, the reference numeral 11 in the figure is a disk, and this disk 1
1 is rotated by a disk motor 12 at a constant linear velocity. An information signal modulated by a self-clocking digital modulation method such as EFM, 3PM, or MFM is recorded on one side of the disk 11, and this information signal is detected by an optical pickup 13 and sent to a preamplifier. The signal is supplied to the pickup servo circuit 15 via 14. This pickup servo circuit 1
6, as is well known, performs tracking servo and focus servo on the pickup 13, and performs feed servo on the pickup feed motor 16.

On the other hand, the analog pulse-like information signal SRF detected by the pickup 13 is sent to the preamplifier 14 and the AGC.
After being preprocessed by the amplifier 17, the data slice circuit 18 performs amplitude discrimination and converts it into a digital information signal SDK. This digital information signal Sos is supplied to a self-synchronous clock regeneration PLL (phase synchronization control) circuit 19, and is also supplied to a data demodulation circuit 21 via a D-type flip 70 tube (hereinafter referred to as D-FF) 20.

Here, the self-synchronous clock regeneration PLL circuit 19 reproduces a self-synchronous clock signal SCK from the digital information signal SD″X, and this clock signal ScK is input to the control input terminal of the D-FF 20 and the data demodulation circuit 21. In other words, the digital information signal SDI is
-At the timing of clock signal ScK by FF20-
The H signal is latched and supplied to the data demodulation circuit 21. This data demodulation circuit 21 receives the self-synchronized clock signal SC
Digital information signal by K, synchronization pattern 5 from SDI
syNc and demodulates, for example, EFM modulation to extract the data signal SDKMO. Both the synchronization pattern detection signal 88YNC and the data signal SDRMO are supplied to the digital signal processing circuit 22.

This digital signal processing circuit 22 receives a clock signal for signal processing from a timing clock generation circuit 27, which will be described later.
5OLK, the data signal SDEMO is subjected to error correction, de-interleave, etc.
This converts EMO into a PCM signal. This PCM
The signal SPCM' is a digital-to-analog converter (hereinafter referred to as DAC).
After being quantized by a circuit 23 (denoted as and outputted to the outside as reproduced audio signals SAR and SAL.

Such a control signal for the operation timing of each circuit is generated by the timing clock generation circuit 27. In other words, this timing clock generation circuit 21 converts the reference clock signal SMCLK supplied via the speed mode changeover switch 28 into a signal processing clock signal 5CLK and a reference clock signal 5R for controlling the rotational speed of the disk motor 12.
FF, LR channel switching control signal SRL, sample and hold timing control signals SR, SL, etc. are generated, and the digital signal processing circuit 22 and the rotation speed control circuit 2 respectively generate them.
9, demultiplexer 24, sample hold circuit 2
5a and 25b. The rotation control circuit 29 transfers the synchronization pattern detection signal 5syNc from the data demodulation circuit 21 to the timing clock generation circuit 27.
Both signals 5syNc are compared with a reference clock signal 5RFF for rotational speed control from 5syNc.

The rotation of the disk motor 12 is controlled to a constant linear velocity through the disk motor drive circuit 30 so that 5RFF always matches.

The speed mode changeover switch 28 is used to switch and set the reproduction speed of the audio signal between normal speed mode and variable speed mode.A crystal oscillator 31 is connected to the fixed terminal A, and a voltage side W is connected to the fixed terminal B. Oscillation circuit (
(hereinafter referred to as ■Co circuit) 32 is connected. That is, when setting the playback speed to normal speed mode, connect the movable terminal C of this switch 28 to the A side and select the clock signal SfO having a predetermined reference frequency fO from the crystal oscillator 31 to clock the timing clock. Generation circuit 27
When setting the variable speed mode, connect the movable terminal C of the switch 28 to the B side to set the vCO
A clock signal Sfv with a set frequency fv is selected from the circuit 32 and is caused to be derived by the timing clock generation circuit 27. A control voltage Vc for setting the oscillation frequency fv of the VCo circuit 32 is generated by a control voltage generation circuit 33 comprising a variable resistor VR to which a reference voltage element V1 is applied and a buffer amplifier Op. In other words, the control voltage generation circuit 33 can freely set the control voltage Vc by moving the sliding terminal of the variable resistor VR by □.

That is, when changing the playback speed, the CD playback device connects the analog switch 28 to the A side to set the variable pull speed mode, adjusts the variable resistance VR of the control voltage generation circuit 33, and changes the control voltage Vc. let At this time, each tIIJIII of the timing clock generation circuit 27
The clock signal frequency changes according to the oscillation frequency fv of the vcO circuit 32, and the disc motor 12 changes accordingly.
Since the rotation of the optical pickup 13 is controlled, the signal detection speed of the optical pickup 13 changes, and the frequency of the self-synchronized clock signal Sc generated by the self-synchronized clock regeneration PLLrgJ path 19 changes accordingly. become. Therefore, the digital information signal SDI is latched and outputted by the D-FF 20 according to the frequency of the self-synchronized clock signal SCK, and is controlled in phase synchronization to the reproduction speed according to the oscillation frequency fv of the vC○ circuit 32.

In the optical digital audio disc playback device as described above, the following conventional self-synchronized clock playback PL
The L circuit 19 will be explained with reference to FIGS. 6 to 8. In addition, FIG. 6 shows its configuration, and FIG. 7 shows the PLLV.
The characteristics of the CO circuit are shown, and FIG. 8 shows each output waveform of the main circuit.

First, in this self-synchronous clock regeneration PLL circuit (hereinafter abbreviated as regeneration PLL circuit) 19, since the digital information signal 5o-t from the data slice circuit 18 does not contain clock information, the edge detection circuit 191 By detecting the rising and falling edges of the digital information signal SD1, a signal S containing clock information is generated.
Generate RC.

Then, the output SRC of this edge detection circuit 191 is converted to a PLLVCO circuit 194 (described later) using a phase comparator 192.
The oscillation output 5vco obtained by the 1/N frequency divider 19
Compare the phase with the signal SpLcg divided by N by 5,
The difference signal ScoMp is supplied to the PLLVCO circuit 194 as a control voltage VcONT via a low-pass filter 193.

Here, the PLLVCO circuit 194 includes resistors R1 to R
5. Zener diode D1, variable capacitance diode D2
, D3, a ramp type LC oscillation circuit 19 consisting of a coil, capacitors C1 to C4, and a transistor Q1.
It is composed of a kiln buffer circuit 19b made up of a1 resistors R6 and R7 and a transistor Q2, and a level conversion circuit 19c made up of a capacitor C5, resistors R8 and R9 and a transistor Q3. The oscillation frequency is variably controlled, the oscillation output is supplied to a level conversion circuit 190 via a buffer circuit 19b, and the level conversion circuit 19c converts it into a signal having a predetermined amplitude level and outputs the signal.

In other words, this regenerative PLL circuit 19 has the same function as the phase comparator 1.
If 92 performs phase comparison using the rising edges of two signals SRc and 5pLcx, the reference signal SRC
A signal is applied to the rising edge phase θRC of Sp L Ox
It operates so that the rising edge phases θPLCK of the signals coincide with each other, and generates a self-synchronizing clock signal Sp LCK.

The self-synchronizing clock signals Sp t and c K are inverted by an inverter 196 and supplied to the clock input terminal CK of the D-FF 20 and the control input terminal of the data demodulation circuit 21 as the self-synchronizing clock signal Sex.

By the way, as shown in FIG. 7, the operating point of the PLLVCO circuit 194 is set so that the lock range and the capture range are approximately equal to each other with respect to the synchronization characteristics of the reproducing PLL circuit 19, that is, the oscillation frequency at the time of synchronization. ing. In the playback PL circuit 19 of the optical digital audio disc playback device, the self-synchronized clock signal frequency at the specified playback speed is set to 4.3218 [Mlhl, and in the case of Fig. 7, it is set to 0 to 10 [V]. The frequency after N division is set to 4.3218 [Mlhl] at the intermediate value 5 [V] of the control voltage VCONT that changes between Frequency f'pLc* of signal Sp L OK
However, the characteristic that fpLcx=4.3218±0.6 [MHz] can be obtained.

Here, the input clock SMCLK of the timing clock generation circuit 27 is changed from a signal SfO of a fixed frequency fO obtained from the crystal oscillator 31 to a VC having an oscillation frequency range of fO±h% by using the speed mode changeover switch 28.
Assume that the output signal Sfv of the O circuit 32 is switched to the variable pull speed mode.

At this time, since the oscillation frequency fv of the CO circuit 32 changes depending on the output voltage Vc of the control voltage generation circuit 33 as described above, the reference clock signal 5RFF of the rotational speed control circuit 29 changes, and the data demodulation circuit 21 The rotational speed and rotational phase of the disk motor 12 are changed so that the synchronous ζ turn detection signal 58YNO obtained from the above is synchronized with the reference clock signal 5RFF. In this case, the playback PLL
The operating point of the PLLVCO circuit 194 of the circuit 19 changes depending on the playback speed. In FIG. 7, the operating points at the maximum and minimum playback speeds when n-6 are indicated by QH and QL.

However, the conventional reproduction PLL circuit 19 as described above
When the operating point of this PLLVCO circuit 194 is Qo or QL, the lock range and capture range cannot be equal above and below the synchronous frequency. If, for example, the playback PLL circuit 19 becomes out of synchronization due to a dropout of the detection signal SRF caused by scratches, dirt, etc. on the signal recording surface of the disk 11, the resynchronization pull-in time will be longer than in the normal speed mode. Alternatively, a problem occurs in which synchronization cannot be performed.

That is, in FIG. 7, the operating point of the PLLVCO circuit 194 is at the QH position, and while the reproduction PLL circuit 19 is operating, synchronization occurs due to dropout, and as a result, the rotational speed of the disk 11 becomes synchronized. If the deviation increases further than before, the digital information signal SDI
The transmission speed will also increase. For this reason, the playback PL
In order to follow this increase, the L circuit 19 increases the control voltage Vco for the PLLVCO circuit 194 corresponding to the phase error.
It operates to further increase N'r from VH, raise the oscillation frequency, and enable synchronous pull-in. However, if the increase in the transmission speed of the input signal SDI is large, the oscillation frequency of the PLLVCO circuit 194 has an upper limit as shown in diagram M7, so the change in the oscillation frequency cannot follow the change in the transmission speed of the input signal SDI. Synchronization becomes difficult. This can be similarly explained even when the operating point of the FiLLVCO circuit 194 is at the VL position.

[Purpose of the Invention] This invention was made to improve the above-mentioned problems, and it is possible to reliably follow the phase synchronization control of the reproduced signal even if dropout of the reproduced signal occurs when the reproduction speed is varied. An object of the present invention is to provide a self-synchronous clock recovery phase synchronization control circuit that can perform self-synchronous clock regeneration and phase synchronization.

[Summary of the Invention] That is, the self-synchronous clock reproduction phase synchronization control circuit according to the present invention reproduces a digital information signal from a digital information signal recording medium, and includes a first voltage-controlled oscillation circuit for generating a reference clock signal. It is used in a digital information signal reproducing device that has a reproduction speed variable function that can vary the reproduction speed of a reproduction signal by changing the oscillation frequency by changing the first control voltage for regenerating the self-synchronized clock from the reproduction signal. and controlling the phase synchronization of the reproduced signal based on the self-synchronized clock signal,
a second voltage controlled oscillation circuit whose oscillation frequency of an output signal changes in accordance with the supplied control voltage; and a phase comparison means which detects a phase difference between the output of the second voltage controlled oscillation circuit and the reproduced signal. and oscillation frequency control means for generating a second control voltage from the signal obtained by the phase comparison means and controlling the oscillation frequency of the second voltage-controlled oscillation circuit by the second control voltage; and second oscillation frequency control means for generating a reverse bias 1IIIJIll voltage from the first control voltage and controlling the oscillation frequency of the second voltage controlled oscillation circuit by the reverse bias control ll voltage. It is characterized by this.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4. However, in FIG. 1, the same parts as in FIGS. 5 and 6 are denoted by the same reference numerals, and only the different parts will be described here.

FIG. 1 shows the configuration when the present invention is applied to the optical digital audio disc playback device.
The ll1lJIIl voltage generation circuit 33 of this optical digital audio disc playback device uses a variable resistor VR with a middle tap, and the middle tap is a fixed terminal of an analog switch 331 that is linked with the analog switch 28 for speed mode switching. A, the sliding terminal is connected to the fixed terminal B, and the voltage derived from the movable terminal C is transferred to the buffer 1.
It is configured to output as a control voltage Vc via an amplifier Op.

In this invention, the control voltage Vc is controlled by the PLLVCO circuit 19.
This is used as a reverse bias voltage to control the oscillation frequency of the Clapp type LC oscillation circuit 194 of No. 4. In other words, this PLLVCO circuit 194 includes resistors R10 to R1.
2, a reverse bias generation circuit 19d generates a reverse bias voltage from the output Vc of the control voltage generation circuit 33;
is provided. And this PLLVCO circuit 19
The oscillation circuit 19a used in 4 includes resistors R1 to R5, a Zener diode D1, and voltage variable capacitance diodes D1 to
D5, one capacitor Q2 and Q3 on the coil, and a transistor Q1. In other words, this oscillation circuit 19
a connects the control voltage VOONT supplied from the low-pass filter 193 to a resistor R1 and a Zener diode D1.
The amplitude is limited so as not to exceed the maximum rating of the voltage variable capacitance diode D2゜D3, and the capacitance of the voltage variable capacitance diode D2゜D3 is increased by supplying the voltage to the voltage variable capacitance diode D2゜D3 via the resistor R2. At the same time, the control voltage Vc from the control voltage generation circuit 33 is supplied to the voltage variable capacitance diode D4D5 via the reverse bias voltage generation circuit 19d, and the voltage variable capacitance diode [+
The capacitance of 4°D5 is controlled.

The operation of the above configuration will be described below with reference to FIGS. 2 and 53.

First, in normal speed mode, analog switch 2
8 and 331 are both closed to the A side, and the output SfO from the crystal oscillator 31 is supplied to the timing clock generation circuit 27. On the other hand, the voltage variable capacitance diode 04.05 of the oscillation circuit 19a is connected to the control voltage generation circuit 33.
The control voltage Vc of +v1/2 is level-adjusted and supplied by the reverse bias voltage generation circuit 19d. At this time, since the control voltage Vc is constant, the oscillation circuit 19
The oscillation frequency of a is controlled only by the control voltage VCONT from the low-pass filter 193.

In the variable speed mode, the analog switches 28 and 331 are both closed to the B side, and the timing clock generation circuit 27 is supplied with the clock signal 3rv from the CO circuit 32. The oscillation frequency fv of this VCO circuit 32 can be controlled by changing the resistance value of the variable resistor VR! Since the pressure \/g changes in the range of 0 to +v1, it changes in a range of ±n% from the center frequency fO.

At the same time, the control voltage Vc is applied to the reverse bias voltage generation circuit 1
Since the voltage is supplied to the voltage variable capacitance diodes D4 and C5 via Vc, the oscillation frequency of the oscillation circuit 19a also changes according to the width of change in the control voltage Vc.

Here, the equal-low circuit of the Clapp type LC oscillation circuit 19a is expressed as shown in FIG. That is, the characteristics of voltage variable capacitance diodes [)2 and [)3 and C4 and C5 are equal, and if the capacitances for arbitrary control voltages VCONT and VC are respectively CvO and Cvl, then capacitors C2 and C3 .

Due to the capacitance of C4 and the inductance of coil L,
The oscillation frequency F is determined by the control voltage Vc to the PLLVCO circuit 194, assuming that the control voltage Vc(7) value, that is, the playback speed is a parameter.
The relationship between ON T and its oscillation frequency is shown in FIG. As can be seen from Fig. 3, the operating point of the PLLVCO circuit 194 can be set at an almost optimal point regardless of changes in playback speed, and as a result, the lock range and capture range can also be set around the frequency at the time of synchronization. This allows the top and bottom to have approximately the same width.

Therefore, the self-synchronized clock regeneration PLL circuit configured as described above can always follow the phase synchronization control even if the transmission speed of the input signal SDI increases or decreases significantly. It is possible to solve problems ranging from out-of-sync due to dropouts to re-synchronization. Furthermore, the circuit configuration is simple and the number of added parts is small.

FIG. 4 shows another embodiment of the present invention, in which a clock signal 5M0LK to be supplied to the timing clock generation circuit 27 is supplied from a PLL frequency synthesizer 34, and an optical digital system employing synthesizer speed control is shown.・This shows the configuration of an audio disc playback device. That is, the PLL frequency synthesizer 34 includes a crystal oscillator 341, a phase comparator 342, a low-pass filter 343, and a synthesizer 700.
It consists of a control circuit 346 having a circuit 344, a program frequency divider 345, and mode changeover switches 81 to S3, and divides the fixed frequency signal from the crystal oscillator 341 and the oscillation output of the synthesizer 700 circuit 344 by the program frequency divider 345. The phase comparator 342 compares the phase of the obtained signal with
3 to a control voltage Vc, and this control voltage Vc controls the oscillation frequency of the synthesizer 700 circuit 344,
The output thereof is supplied to the timing clock generation circuit 21. The program frequency divider 345 is set to a specified frequency division ratio when the normal speed mode is designated by the mode changeover switches 81 to S3 of the control circuit 346, and is set to a specified frequency division ratio when the up speed mode or down speed mode is designated. Accordingly, the frequency division ratio is changed sequentially from the specified frequency division ratio. Therefore, the control voltage V generated by the low-pass filter 343
By supplying the voltage to the voltage variable capacitance diodes D4 and C5 via the reverse bias voltage generation circuit 19d of the PLLVCO circuit 194, the same effect as in the above embodiment can be obtained.

[Effects of the Invention] As detailed above, the present invention provides a self-synchronizing clock that can reliably follow the phase synchronization control of the reproduced signal even if a dropout of the reproduced signal occurs when the reproduction speed is varied. , a regeneration phase synchronization control circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of a self-synchronized clock regeneration phase synchronization control circuit according to the present invention, FIG. FIG. 4 is a block circuit diagram showing another embodiment of the invention, and FIG. 5 is an optical digital audio disc to which the invention is applied. FIG. 6 is a block circuit diagram showing the configuration of a reproducing device. FIG. 6 is a block circuit diagram showing the configuration of a conventional self-synchronous clock regeneration phase synchronization control circuit. FIG. 7 shows the characteristics of the Clapp type LC oscillation circuit used in the conventional example. The characteristic diagram shown in FIG. 8 is a waveform diagram showing each output waveform of the main parts of the conventional example. 19...Self-synchronized clock regeneration PLL circuit, 191.
... Edge detection circuit, 192 ... Phase comparator, 193
...Low pass filter, 194...PLLVCO circuit, 195...1/N frequency divider, 196...Inverter, 19a...Clap type LC oscillation circuit, 19b...
・Buffer circuit, 19c...Level conversion circuit, 19d
...Reverse bias voltage generation circuit, 20...D-FF,
21... Data demodulation circuit, 22... Digital signal processing circuit, 27... Timing clock generation circuit, 28
...Speed mode changeover switch, -31...Crystal oscillator, 32...VCO circuit, 33...Control voltage generation circuit, Vc, VcoNr...Control voltage.

Claims (1)

[Claims] This device reproduces a digital information signal from a digital information signal recording medium, and changes the oscillation frequency by changing the first control voltage for the first voltage-controlled oscillation circuit for generating the reference clock signal. A self-synchronizing clock used in a digital information signal reproducing device having a variable reproduction speed function capable of varying the reproduction speed, reproducing a self-synchronizing clock from a reproduced signal and controlling phase synchronization of the reproduced signal based on the self-synchronizing clock signal. a second voltage controlled oscillation circuit in which the oscillation frequency of the output signal changes in response to the supplied control voltage in the regenerative phase synchronization control circuit;
a phase comparison means for detecting a phase difference between the output of the second voltage controlled oscillator circuit and the reproduced signal; and a second control voltage that is generated from the signal obtained by the phase comparison means. a first oscillation frequency control means for controlling the oscillation frequency of the second voltage controlled oscillator circuit; 1. A self-synchronous clock regeneration phase synchronization control circuit comprising: second oscillation frequency control means for controlling the oscillation frequency of the voltage controlled oscillation circuit.